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| a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 1 this document is a general product de scription and is subject to change without notice. hynix semiconductor does not assume any responsibility for use of circuits described. no patent licenses are implied. h5tq2g63bfr 2gb ddr3 sdram lead-free&halogen-free (rohs compliant) h5tq2g63bfr ** contents are subject to change at any time without notice. *33ed5962-ee6c* b20337/178.104.2.234/2010-08-26 09:03
a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 2 h5tq2g63bfr revision history revision no. history page draft date remark 0.1 preliminary initial release sep. 2009 preliminary 0.2 added mode register (mr0, mr1, mr2,mr3, mpr) oct. 2009 0.3 added idd value(all items) @800/9000mhz changed ac timing(nrcd, nrc, nras, nrp) @800mhz changed speed bin(cl, cwl & min/max timing ) @800/900mhz, 1.0ghz 65 56 67 ~69 nov.2009 0.4 corrected typo and wording changed single ended ac and dc input levels table updated ac overshoot/undershoot specification for 1ghz added timings for 900mhz/1.0ghz(table1) changed & updated idd specification table changed speed bin for 800/900mhz/1.0ghz changed electrical characteristics and ac timing all 34 42 56 65 67~69 71~77 may. 2010 0.5 changed speed bin for 800/900mhz 67,68 aug. 2010 *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w z a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 3 h5tq2g63bfr table of contents 1. description 1.1 device features and ordering information 1.1.1 features 1.1.2 ordering information 1.2 package ballout / mechanical dimension 1.2.1 x16 package ball out 1.3 row and column address table: 2g 1.4 pin functional description 1.5 programming the mode register 1.6 mode register(mr0) 1.6.1 burst length, type and order 1.6.2 cas latency 1.6.3 test mode 1.6.4 dll reset 1.6.5 write recovery 1.6.6 precharge pd dll 1.7 mode register(mr1) 1.7.1 dll enable/disable 1.7.2 output driver impedance control 1.7.3 odt rtt values 1.7.4 additive latency(al) 1.7.5 write leveling 1.7.6 output disable 1.8 mode register(mr2) 1.8.1 partial array self-refresh(pasr) 1.8.2 cas write latency(cwl) 1.8.3 auto self-refresh(asr) and self-refresh temperature(srt) 1.8.4 dynamic odt(rtt_wr) 1.9 mode register(mr3) 1.10 multi-purposer register(mpr) 1.10.1 multi purpose register 1.10.2 mpr functional description 1.10.3 mpr register address definition 1.10.4 relevant timing parameters 1.10.5 protocol example *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w z a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 2. command description 2.1 command truth table 2.2 clock enable (cke) truth table for synchronous transitions 3. absolute maximum ratings 4. operating conditions 4.1 operating temperature condition 4.2 dc operating conditions 5. ac and dc input measurement levels 5.1 ac and dc logic input levels for single-ended signals 5.2 ac and dc logic input levels for differential signals 5.3 differential input cross point voltage 5.4 slew rate definitions for single ended input signals 5.4.1 input slew rate for input setup time (tis) and data setup time (tds) 5.4.2 input slew rate for input hold time (tih) and data hold time (tdh) 5.5 slew rate definitions for differential input signals 6. ac and dc output measurement levels 6.1 single ended ac and dc output levels 6.1.1 differential ac and dc output levels 6.2 single ended output slew rate 6.3 differential output slew rate 6.4 reference load for ac timing and output slew rate 7. overshoot and undershoot specifications 7.1 address and control overshoo t and undershoot specifications 7.2 clock, data, strobe and mask ov ershoot and undershoot specifications 7.3 34 ohm output driver dc electrical characteristics 7.4 output driver temperature and voltage sensitivity *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w z a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 5 h5tq2g63bfr 7.5 on-die termination (odt) levels and i-v characteristics 7.5.1 on-die termination (odt) levels and i-v characteristics 7.5.2 odt dc electrical characteristics 7.5.3 odt temperature and voltage sensitivity 7.6 odt timing definitions 7.6.1 test load for odt timings 7.6.2 odt timing reference load 8. idd specification parameters and test conditions 8.1 idd measurement conditions 8.2 idd specifications 8.2.1 idd6 current definition 8.2.2 idd6tc specification (see notes 1~2) 9. input/output capacitance 10. standard speed bins 11. electrical characteristics and ac timing 12. package dimensions *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w z a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 6 h5tq2g63bfr 1. 1.1 . 1 0 o c~ 95 o c) - 7.8 s at 0 o c ~ 85 o c - 3.9 s at 85 o c ~ 95 o c ? auto self refresh supported ? jedec standard 96ball fbga(x16) ? driver strength selected by emrs ? dynamic on die termination supported ? asynchronous reset pin supported ? zq calibration supported ? write levelization supported ? on die thermal sensor supported ? 8 bit pre-fetch 1.1 2 20331.10.2.23201002 0:03 a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 7 h5tq2g63bfr 1.2 package ball out 1.2.1 x16 package ball out note: green nc balls indicate mechanical support balls with no internal connection 1 2 3 4 5 6 7 8 9 a vddq dqu5 dqu7 dqu4 vddq vss a b vssq vdd vss dqsu dqu6 vssq b c vddq dqu3 dqu1 dqsu dqu2 vddq c d vssq vddq dmu dqu0 vssq vdd d e vss vssq dql0 dml vssq vddq e f vddq dql2 dqsl dql1 dql3 vssq f g vssq dql6 dqsl vdd vss vssq g h vrefdq vddq dql4 dql7 dql5 vddq h j nc vss ras ck vss nc j k odt vdd cas ck vdd cke k l nc cs we a10/ap zq nc l m vss ba0 ba2 a15 vrefca vss m n vdd a3 a0 a12/bc ba1 vdd n p vss a5 a2 a1 a4 vss p r vdd a7 a9 a11 a6 vdd r t vss reset a13 nc a8 vss t 1 2 3 4 5 6 7 8 9 populated ball ball not populated back view 1 a b c d e f g h j k l m n populated ball ball not populated 2 789 (top view: see the balls through the package) 3 p r t *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w z a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 8 h5tq2g63bfr 1.3 row and column address table 2gb note1: page size is the number of bytes of data delive red from the array to the internal sense amplifiers 8 where colbits = the number of column address bits, org = the number of i/o (dq) bits configuration 128mb x 16 # of banks 8 bank address ba0 - ba2 auto precharge a10/ap bl switch on the fly a12/bc row address a0 - a13 column address a0 - a9 page size 1 2 kb *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w z a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 9 h5tq2g63bfr 1.4 pin functional description 1.4 pin functional description symbol type function ck, ck input clock: ck and ck are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck . cke input clock enable: cke high activates, and cke low de activates, internal clock signals and device input buffers and output drivers. taking cke low provides precharge power-down and self- refresh operation (all banks idle), or active power-down (row active in any bank). cke is asynchronous for self-refresh exit. af ter vrefca and vrefdq have become stable during the power on and initia lization sequence, they must be maintained during all operations (including self-refresh). cke must be maintained high throughout read and write accesses. input buffers, excluding ck, ck , odt and cke are disabled during power-down. input buffers, excluding cke, ar e disabled during self-refresh. cs input chip select: all commands are masked when cs is registered high. cs provides for external rank selection on systems with multiple ranks. cs is considered part of the command code. odt input on die termination: odt (registered high) enab les termination resistance internal to the ddr3 sdram. when enabled, odt is only applied to each dq, dqs, dqs and dm/tdqs, nu/ tdqs (when tdqs is enabled via mode register a11=1 in mr1) signal for x4/x8 configurations. for x16 configuration odt is applied to each dq, dqsu, dqsu , dqsl, dqsl , dmu, and dml signal. the odt pin will be ignored if mr1 is programmed to disable odt. ras . cas . we input command inputs: ras , cas and we (along with cs ) define the command being entered. dm, (dmu), (dml) input input data mask: dm is an input mask signal fo r write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs. for x8 device, the function of dm or tdqs/tdqs is enabled by mode register a11 setting in mr1. ba0 - ba2 input bank address inputs: ba0 - ba2 define to which bank an active, read, write or precharge command is being applied. bank address also determines if the mode register or extended mode register is to be accessed during a mrs cycle. a0 - a15 input address inputs: provide the row address for active commands and the column address for read/write commands to select one location ou t of the memory array in the respective bank. (a10/ap and a12/bc have additional functions, see below). the address inputs also provide the op-c ode during mode register set commands. a10 / ap input auto-precharge: a10 is sampled during re ad/write commands to determine whether autoprecharge should be performed to the acce ssed bank after the read/write operation. (high: autoprecharge; low: no autoprecharge).a10 is sampled during a precharge command to determine whether the precharge a pplies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharg ed, the bank is selected by bank addresses. a12 / bc input burst chop: a12 / bc is sampled during read and write commands to determine if burst chop (on-the-fly) will be performed. (high, no burst chop; low: burst choppe d). see command truth table for details. reset input active low asynchronous reset: reset is active when reset is low, and inactive when reset is high. reset must be high during normal operation. reset is a cmos rail to rail signal with dc high and low at 80% and 20% of v dd , i.e. 1.20v for dc high and 0.30v for dc low. *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w z a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 10 h5tq2g63bfr dq input / output data input/ output: bi -directional data bus. dqu, dql, dqs, dqs , dqsu, dqsu , dqsl, dqsl input / output data strobe: output with read data, input wi th write data. edge-aligned with read data, centered in write data. for the x16, dqsl co rresponds to the data on dql0-dql7; dqsu corresponds to the data on dqu0-dqu7. the da ta strobe dqs, dqsl, and dqsu are paired with differential signals dqs , dqsl , and dqsu , respectively, to provide differential pair signaling to the system during reads and writes. ddr3 sdram supports differential data strobe only and does not support single-ended. nc no connect: no internal elec trical connection is present. v ddq supply dq power supply: 1.5 v +/- 0.075 v v ssq supply dq ground v dd supply power supply: 1.5 v +/- 0.075 v v ss supply ground v refdq supply reference voltage for dq v refca supply reference voltage zq supply reference pin for zq calibration note: input only pins (ba0-ba2, a0-a15, ras , cas , we , cs , cke, odt, dm, and reset ) do not supply termination. symbol type function *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w z a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 11 h5tq2g63bfr 1.5 programming the mode registers for application flexibility, various fu nctions, features and mo des are programmable in four mode registers, provided by the ddr3 sdram, as user defined variables and they must be programmed via a mode register set (mrs) command. as the default values of the mode registers (mr#) are not defined, contents of mode registers must be fully initialized and/ or re-initialized, i.e. written, afte r power-up and/or reset for proper oper- ation. also the conten ts of the mode registers can be altered by re-executing the mrs command during nor- mal operation. when programming the mode registers, even if the user ch ooses to modify only a sub-set of the mrs fields, all address fields within the accessed mode register must be redefined when the mrs com- mand is issued. mrs command and dll reset do not a ffect array contents, whic h means these commands can be executed any time after power-up without affecting the array contents. the mode register set command cylce time, tmrd is required to complete the write operation to the mode regsiter and is the minimum time required between two mrs commands shown in figure 4. figure 4. tmrd timing the mrs command to non-mrs command delay, tmod, is required for the dram to update the features, except dll reset, adn is the minimum time required from an mrs command to a non-mrs command exclud- ing nop and des shown in figure 5. address t0 ck# ck t1 t2 ta0 ta1 tb0 tb1 tb2 tc0 tc1 tc2 mrs valid mrs valid old settings time break don ? t care cmd cke valid valid valid nop /des nop /des nop /des nop /des valid valid valid valid valid valid valid valid valid valid valid updating settings new settings valid valid valid valid valid valid valid valid valid valid valid valid valid valid tmrd tmod rtt_nom disenabled prior and/or after mrs command rtt_nom enabled prior and/or after mrs command odtloff+1 setting odt odt *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w z a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 12 h5tq2g63bfr figure 5. tmod timing the mode register contents can be changed using th e same command and timing requirements during nor- mal operation as long as the dram in in idle state, i.e. all banks are in the precharged state with trp satis- fied, all data bursts are completed and cke is high pr ior to writing into the mode register. if the rtt_nom feature is enabled in the mode register prior and/or after an mrs commnad, the odt signal must comtinu- ously be registered low ensuring rtt is in an off stated prior to the mrs command. the odt signal may be registered high after tmod has expired. if the rtt_nom feature is disabled in the mode register prior and after an mrs command, the odt signal can be regist red either low or high before, during and after the mrs command. the mode registers are divided into various fields depending on the functionality and/or modes. t0 ck# ck address t1 t2 ta0 ta1 ta2 ta3 ta4 tb0 tb1 tb2 mrs valid valid old settings time break don ? t care cmd cke seetings odt valid valid nop /des nop /des nop /des nop /des valid updating settings new settings valid valid valid valid valid valid valid valid valid valid valid valid valid valid odt tmod nop /des valid valid valid valid valid valid valid valid valid valid valid odtloff+1 rtt_nom disenabled prior and/or after mrs command rtt_nom enabled prior and/or after mrs command *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w z a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 13 h5tq2g63bfr 1.6 mode register mr0 the mode register stores the data for controlling the various operating modes of ddr3 sdram. it controls burst length, read burst type, cas la tency, test mode, dll reset, wr and dll control for precharge power- down, which include various vendor specific options to make ddr3 sdram useful for various applicatons. the mode register is written by asserting low on cs, cas, we, ba0 , ba1, and ba2, while controlling the states of address pins according to figure 6. address field a6 a5 a4 a2 cas latency 0000 reserved 0010 5 0100 6 0110 7 1000 8 1010 9 1100 10 1110 11 0001 12 0011 13 0101 14 a7 mode 0normal 1test a3 read burst type 0 sequential 1 interleave a8 dll reset 0no 1yes mode register 0 ba 1 ba 0 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 0 tm cas latency rbt dll 0* 1 wr write recovery for autoprecharge a11 a10 a9 wr(cycles) 000 16 *2 001 5 *2 010 6 *2 011 7 *2 100 8 *2 101 10 *2 110 12 *2 111 14 *2 a 15 ~ a 13 0 cl a2 a1 bl 0 1 8 (fixed) 0 1 bc4 of 8(on the fly) 1 0 bc4 (fixed) 11 reserved *1 : ba2 and a13~a15 are rfu and must be programmed to 0 during mrs. *2: wr(write recovery for autoprecharge) mi n in clock cycles is calc ulated by dividing twr(in ns ) by tck(in ns) and rounding up to the next integer: wrmin[cycles] = roundup(twr[ns]/tck[ns]) . the wr value in the mode register must be programmed to be equal or larger t han wrmin. the programmed wr value is used with trp to determine tdal. *3: the table only shows the encodings for a given cas latency. for actual supported cas latency, please refer to speedbin tabl es for each frequency. *4: the table only shows the encodings for wr ite recovery. for actual write recovery timing, please refer to ac timing table. ba 2 0* 1 ba1 ba0 mr select 00 mr0 01 mr1 10 mr2 11 mr3 a 12 ppd a12 dll control for precharge pd 0 slow exit (dll off) 1 fast exit (dll on) figure 6. ddr3 sdram m ode register set (mr0) bl a1 a0 bl 0 1 8 (fixed) 0 1 bc4 of 8(on the fly) 1 0 bc4 (fixed) 11 reserved *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w z a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 14 h5tq2g63bfr 1.6.1 burst length, type and order accesses within a given burst may be progra mmed to suquential or interleaved order. the burst type is selected via bit a3 as shown is figure 6. the ordering of accesses within a burst is determined by the burst lengt h, burst type, and the start- ing column address as shown in table 2. the burst length is defined by bits a0-a1. burst length options include fixed bc4, fixed bl8, and ?on the fly? which allows bc4 or bl8 to be selected coincident with the registration of a read or write command via a12/bc . table 2. burst type and burst order burst length read/ write starting column address (a2,a1,a0) burst type = sequential (decimal) a3 = 0 burst type = interleaved (decimal) a3 = 1 notes 4 chop read 0 0 0 0,1,2,3,t,t,t,t 0,1,2,3,t,t,t,t 1,2,3 0 0 1 1,2,3,0,t,t,t,t 1,0,3,2,t,t,t,t, 1,2,3 0 1 0 2,3,0,1,t,t,t,t 2,3,0,1,t,t,t,t 1,2,3 0 1 1 3,0,1,2,t,t,t,t 3,2,1,0,t,t,t,t 1,2,3 1 0 0 4,5,6,7,t,t,t,t 4,5,6,7,t,t,t,t 1,2,3 1 0 1 5,6,7,4,t,t,t,t 5,4,7,6,t,t,t,t 1,2,3 1 1 0 6,7,4,5,t,t,t,t 6,7,4,5,t,t,t,t 1,2,3 1 1 1 7,4,5,6,t,t,t,t 7,6,5,4,t,t,t,t 1,2,3 write 0,v,v 0,1,2,3,x,x,x,x 0,1,2,3,x,x,x,x 1,2,4,5 1,v,v 4,5,6,7,x,x,x,x 4,5,6,7,x,x,x,x 1,2,4,5 8 read 0 0 0 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7 2 0 0 1 1,2,3,0,5,6,7,4 1,0,3,2,5,4,7,6 2 0 1 0 2,3,0,1,6,7,4,5 2,3,0,1,6,7,4,5 2 0 1 1 3,0,1,2,7,4,5,6 3,2,1,0,7,6,5,4 2 1 0 0 4,5,6,7,0,1,2,3 4,5,6,7,0,1,2,3 2 1 0 1 5,6,7,4,1,2,3,0 5,4,7,6,1,0,3,2 2 1 1 0 6,7,4,5,2,3,0,1 6,7,4,5,2,3,0,1 2 1 1 1 7,4,5,6,3,0,1,2 7,6,5,4,3,2,1,0 2 write v,v,v 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7 2,4 notes: 1. in case of burst length being fixed to 4 by mr0 setting, the internal write operation starts two clock cycles earlier than for the bl8 mode. this means t hat the starting point for twr and twtr will be pulled in by two clocks. in case of burst length being sele cted on-the-fly via a12/bc#, the internal write opera- tion starts at the same point in time like a burst of 8 write operation. this means that during on-the-fly control, the starting poin t for twr and twtr will not be pulled in by two clocks. 2. 0...7 bit number is value of ca[2:0] that causes this bit to be the fi rst read during a burst. 3. t: ouput driver ofr data and strobes are in high impedance. 4. v: a valid logic level (0 or 1), but respective buffer input ignores level on input pins. 5. x: don?t care. *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w z a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 15 h5tq2g63bfr 1.6.2 cas latency the cas latency is defined by mr0 (bits a9-a11) as shown in figure 6. cas latency is the delay, is clock cycles, between the internal read command and the availability of the first bit of output data. ddr3 sdram does not support any half clock latencies. the overall read latency (rl) is defined as additive latency (al) + cas latency (cl); rl = al + cl. for more information on the supported cl and al sett ings based on the operating clock frequency, refer to ?stan- dard speed bins? . for detailed read operation refer to ?read operation?. 1.6.3 test mode the normal operating mode is selected by mr0 (bit a7 = 0) and all other bits set to the desired values shown in figure 6. programming bit a7 to a ?1? places the ddr3 sdram into a test mode that is only used by the dram manufacturer and should not be used. no operations or functionality is specified if a7 = 1. 1.6.4 dll reset the dll reset bit is self-clearing, meaning it returns back to the value of ?0? after the dll reset function has been issued. once the dll is enabled, a subsequent dll reset should be applied. any time the dll reset function is used, tdllk must be met before any functions that require the dll can be used (i.e. read commands or odt synchronous opera- tions.). 1.6.5 write recovery the programmed wr value mr0 (bits a9, a10, and a11) is used for the auto precharge feature along with trp to deter- mine tdal wr(write recovery for auto-precharge)min in clock cycles is calculated by dividing twr(in ns) by tck(in ns) and rounding up to the next integer: wrmin[cycles] = ro undup(twr[ns]/tck[ns]). the wr must be programmed to be equal or larger than twr(min). 1.6.6 precharge pd dll mr0 (bit a12) is used to select the dll usage during pr echarge power-down mode. when mr 0 (a12 = 0), or ?slow-exit?, the dll is frozen after entering precharge power-down (for potential power savings) and upon exit requires txpdll to be met prior to the next valid command. when mr0 (a12 = 1), or ?fast-exit?, the dll is mainta ined after entering precharge power-down requires txp to be met prior to the next vaild command. *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w z a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 16 h5tq2g63bfr address field tdqs mode register 1 dll 0* 1 d.i.c ba 0 a 15 ~ a 13 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a 0 dll enable 0 enable 1 disable al a7 write leveling enable 0 disabled 1 enabled 1 0* 1 rtt_nom note: rzq= 240 ? a5 a1 output driver impedence control 00 rzq/6 01 rzq/7 10 rzq/tbd 11 rzq/tbd a 4 a 3 additive latency 0 0 0 (al disabled) 01 cl-1 10 cl-2 11 reserved *1 : ba2 and a8, a10, and a13~a15 are rfu and must be programmed to 0 during mrs. ba 1 0 a9 a6 a2 rtt_nom *3 0 0 0 rtt_nom disabled 0 0 1 rzq/4 0 1 0 rzq/2 0 1 1 rzq/6 100 rzq/12 *4 101 rzq/8 *4 1 1 0 reserved 1 1 1 reserved a11 tdqs enable 0 disabled 1 enabled ba 2 0* 1 1.7 mode register mr1 the mode register mr1 stores the data for enabling of disabling the dll, output driver strength, rtt_nom impedance, additive latency, write leveling enable, tdqs enable and qoff. the mode register 1 is written by asserting low on cs , ras , cas , we , high on ba0 and low on ba1 and ba2, while controlling the states of address pins according to figure 7. qoff a 12 *2: outputs disabled - dqs, dqss, dqs#s. a 12 qoff *2 0 output buffer enabled 1 output buffer disabled *2 figure 7. mr1 definition d.i.c rtt_nom level 0* 1 rtt_nom note: rzq = 240 ? *3: in write leveling mode (mr1[bit7]=1) with mr1[bit12]=1, all rtt_nom settings are allowed; in write leveling mode (mr1[bit7]=1) with mr1[bit12]=0, only rtt_nom settings of rzq/2, rzq4 and rzq/6 are allowed. *4: if rtt_nomm is used during writes, only the val- ues rzq/2,rzq/4 and rzq/6 are allowed. ba1 ba0 mr select 00 mr0 01 mr1 10 mr2 11 mr3 *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w z a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 17 h5tq2g63bfr 1.7.1 dll enable/disable the dll must be enabled for normal operation. dll enable is required during power up initialization, and upon returning to normal operation after having the dll disabled. during norm al operation (dll-on) with mr1 (a0 = 0), the dll is auto- matically disabled when entering self-refresh operation and is automatically re-enabled upon exit of self-refresh opera- tion. any time the dll is enabled and subsequently reset, td llk clock cycles must occur be fore a read or synchronous odt command can be issued to allow time for the internal clock to be synchronized with the external clock. failing to wait for synchronization to occur may result in a violation of th e tdqsck, taon or taof parameters. during tdllk, cke must continuously be registered high. ddr3 sdram does not requir e dll for any write operation, except when rtt_wr is enabled and the dll is required for proper odt operation. fo r more detailed information on dll disable operation refer to ?dll-off mode? on page 37. the direct odt feature is not supported during dll-off mode . the on-die termination resistors must be disabled by con- tinuously registering the odt pin low and/ or by programming the rtt_nom bits mr1{a9,a6,a2} to {0,0,0} via a mode register set command during dll-off mode. the dynamic odt feature is not supp orted at dll-off mode. user must use mrs command to set rtt_wr, mr2 {a10, a9} = {0,0}, to disable dynamic odt externally. 1.7.2 output driver impedance control the output driver impedance of the ddr 3 sdram device is selected by mr1 (bits a1 and a5) as shown in figure 7. 1.7.3 odt rtt values ddr3 sdram is capable of providing two different terminat ion values (rtt_nom and rtt_wr). the nominal termination value rtt_nom is programmed in mr1. a seperate value (rtt_wr) may be programmed in mr2 to enable a unique rtt value when odt is enabled during writes. the rtt_wr value can be applied during writes even when rtt_nom is dis- abled. 1.7.4 additive latency (al) additive latency (al) operation is supported to make co mmand and data bus dfficient for sustainable bandwidths in ddr3 sdram. in this operation, the ddr3 sdram allows a read or write command (either with or without auto-pre- charge) to be issued immediately after the active command. the command is held for the time of the additive latency (al) before it is issued inside the device. the read latency (r l) is controlled by the sum of the al and cas latency (cl) register settings. write latency (wl) is controlled by the sum of the al and cas write latency (cwl) register settings. a summary of the al register options are shown in table. 1.7.5 write leveling for better signal integrity, ddr3 memory module adopted fly-by topology for the commands, addresses, control signals and clocks. the fly-by topology has benefits from reducing num ber of stubs and their length but in other aspect, caused flight time skew between clock and strobe at every dram on di mm. it makes it difficult ofr the controller to maintain tdqss, tdss and tdsh specification. th erefore, the ddr3 sdram supports a ?wri te leveling? feature to allow the con- troller to compensate for skew. see ?write leveling? for mode details. table 3. additive la tency (al) settings note : al has a value of cl - 1 or cl - 2 as per the cl values programmed in the mr0 register a4 a3 al 0 1 0 (al disabled) 01 cl - 1 10 cl - 2 11reserved *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w z a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 18 h5tq2g63bfr 1.7.6 output disable the ddr3 sdram oupputs may be enabled/disabled by mr1 (bit a12) as shown in figure 7. when this feature is enabled (a12=1), all output pins (dqs, dqs, dqs , etc.) are disconnected from the device removing any loading of the output drivers. this feature may be us eful when measuring module power for example. for normal operation, a12 should be set to ?0?. *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w z a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 19 h5tq2g63bfr 1.8 mode register mr2 the mode register mr2 stor es the data for controlling refresh rela ted features, rtt_wr impedance, and cas wire latency.the mode register 2 is written by a sserting low on cs , ras , cas , we , high on ba1 and low on ba0 and ba2, while controlling the states of address pins according to the table below. mr2 programming: *1 : ba2, a5, a8, a11~a15 are rfu and must be programmed to 0 during mrs. *2 : the rtt_wr value can be applied during wirtes even when rtt_no m is disabled. during write leve ling, dynamic odt is not ava ilable. address field mode register 2 0* 1 ba 0 a 15 ~ a 13 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 0 ba 1 1 ba 2 0* 1 a 12 rtt_wr 0* 1 pasr cwl srt asr ba1 ba0 mr mode 00 mr0 01 mr1 10 mr2 11 mr3 a2 a1 a0 partial array self refresh (optional) 0 0 0 full array 0 0 1 half array (ba[2:0]=000,001,010&011) 0 1 0 quarter array (ba[2:0]=000&001) 0 1 1 1/8th array (ba[2:0]=000) 1 0 0 3/4 array (ba[2:0]=010,011,100,101,110&111) 1 0 1 half array (ba[2:0]=100,101,110&111) 1 1 0 quarter array (ba[2:0]=110&111) 1 1 1 1/8th array (ba[2:0]=111) a10 a9 rtt_wr * 2 00 dynamic odt off(write does not affect rtt value) 01 rzq/4 10 rzq/2 11 reserved a6 auto-self-refresh (asr) 0 manual sr reference (srt) 1 asr enable (optional) figure 8. mr2 definition a7 self-refresh temperature (srt) range 0 normal operating temperature range 1 extended (optional) operating temperature range a5 a4 a3 cas wirte latency (cwl) 000 5 (tck(avg) 2.5ns) 001 6 (2.5ns>tck(avg 1.875ns) 010 7 (1.875ns tck(avg) 1.5ns) 011 8 (1.5ns tck(avg) 1.25ns) 100 9 (1.25ns tck(avg) 1.0ns) *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w z a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 20 h5tq2g63bfr 1.8.1 partial array self-refresh (pasr) optional in ddr3 sdram: users should refer to the dram supplier data sheet and/or the dimm spd to detemine if ddr3 sdram devices support the following options or requirem ents referred to in this material. if pasr (partial array self-refresh) is enabled, data located in areas of the array beyond the specif ied address range shown in figure 8 wil be maintains if trefi conditions are met and no self-refresh command is issued. 1.8.2 cas write latency (cwl) the cas write latency is defined by mr2 (bits a3-a5), as sh own in figure 8. cas write latency is the delay, in clock cycles, between the internal writ e command and the availability of the first bit of in put data. ddr3 s dram does not sup- port any half clock latencies. the overall write latency (wl) is defined as additive latency (al) + cas write latency (cwl); wl = al + cwl. for detailed writ e operation refer to ?write operation?. 1.8.3 auto self-refresh (asr) a nd self-refresh temperature (srt) optional in ddr3 sdram: users should refer to the dram supplier data sheet and/or the dimm spd to determaine if ddr3 sdram devices support the following options or require ments referred to in this material. ddr3 sdram?s must support self-refresh operation at all s upported temperatures. applications re quiring self-refresh operation in the extended temperature range must use the optional asr function or program the srt bit appropriately. 1.8.4 dynamic odt (rtt_wr) ddr3 sdram introduces a new feature ?d ynamic odt?. in certain application cases and to further enhance signal integ- rity on the data bus, it is desirable th at the termination strength of the ddr3 sdram can be changed without issuing an mrs command. mr2 register locations a9 and a10 configure the dynamic odt setings. in write leveling mode, only rtt_nom is available. for details on dynamic odt operation, refer to ?dynamic odt?. *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w z a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 21 h5tq2g63bfr 1.9 mode register mr3 the mode register mr3 controls multi purpose registers. the mode register 3 is written by asserting low on cs , ras , cas , we , high on ba1 and ba0, and low on ba2 while controlling the states of address pins according to the table below. mr3 programming: *1 : ba2, a3-a15 are rfu and must be programmed to 0 during mrs. *2 : the predefined pattern will be used for read synchronization. *3 : when mpr control is set for normal operation (mr3 a[2]=0) then mr3 a[1:0] will be ignored. 1.10 multi-purpose register (mpr) the multi purpose register(mpr) function is used to read ou t a predefined system timing calibration bit sequence. to enable the mpr, a mode register set(mrs) command must be issued to mr3 register with bit a2=1. prior to issuing the mrs command, all banks must be in the idle state (all banks precharged and trp met). once the mpr is enabled, any subsequent rd or rda commands will be redirected to the multi purpose register. when the mpr is enabled, only rd ro rda commands are allowed until a subsequent mrs co mmand is issued with the mpr disabled(mr3 bit a2=0). power-down mode, self-refresh, and any other non-rd/rda command is not allowed during mpr enable mode. the reset function is supported during mpr enable mode. for detailed mpr operation refer to ?multi purpose register?. 0* 1 ba 0 a 15 ~ a 13 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 1 ba 1 1 ba 2 0* 1 a 12 address field mode register 3 mpr loc mpr figure 9. mr3 definition ba1 ba0 mr select 00 mr0 01 mr1 10 mr2 11 mr3 mpr operation a2 mpr * 2 0 normal operation* 3 1 dataflow from mpr mpr address a1 a0 mpr location 00 predefined pattern* 2 01 rfu 10 rfu 11 rfu *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w z a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 22 h5tq2g63bfr 1.10.1 multi purpose register the multi purpose register (mpr) function is used to read out a predefined system timing calibration bit sequence. the basic concept of the mpr is shown in figure 10. figure 10. mpr block diagram the enable the mpr, a mode register set (mrs) comm and must be issued to mr3 register with bit a2=1, as shown in table 5. prior to issuing the mrs command, all banks must be in the id le in the idle state (all banks precharged and tr p met). once the mpr is enabled, any subsequent rd or rda commands will be redirected to the multi purpose register. the result ing operation when a rd or rda command is issued is defined by mr3 bits a[1:0] when the mpr is enabled as shown in table 6. when the mpr is enabled, only rd or rda commands are allowed until a subsequent mrs command is issued with the mpr disabled(mr3 bit a2=0). note that in mpr mode rda has the same functionality as a read command which means the auto precharge part of rda is ignored. power-down mode, self-refresh, and any other non-rd/rda com- mand is not allowed during mpr enable mode. the reset function is supported during mpr enable mode. memory core (all banks precharged) multi purpose register pre-defined data for reads dq, dm, dqs, dqs# mr3[a2] table 5. mpr mr3 register definition mr3 a[2] mr3 a[1:0] function mpr mpr-loc 0b don?t care (0b or 1b) normal operation, no mpr transaction. all subsequent reads will come from dram array. all subsequent write will go to dram array. 1b see table 12 enable mpr mode, subsequent rd/rda commands defined by mr3 a[1:0] *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w z a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 23 h5tq2g63bfr 1.10.2 mpr functional description ? one bit wide logical interface via all dq pins during read operation. ? register read on x16: ? dql[7:1] and dqu[7:1] either drive the sa me information as dq[0], or they drive 0b. ? addressing during for multi purpose register reads for all mpr agents: ? ba[2:0]: don?t care ? a[1:0]: a[1:0] must be equal to ?00?b.da ta read burst order in nibble is fixed. ? a[2]: for bl=8, a[2] must be equal to 0b, burst order is fixed to [0,1,2,3,4,5 ,6,7],* for burst chop 4 cases, the burst order is switched on nibble base a[2]=0b, burst order: 0,1,2,3* a[2]=1b, burst order: 4,5,6,7* ? a[9:3]: don?t care ? a10/ap: don?t care ? a12/bc: selects burst chop mode on-the-fly, if enabled within mr0. ? a11,a13,...(if available): don?t care ? regular interface functionality during register reads: ? support two burst ordering which are switched with a2 and a[1:0]=00b. ? support of read burst chop (mrs and on-the-fly via a12/bc) ? all other address bits (r emaining column address bits includi ng a10, all bank address bits) will be ignored by the ddr3 sdram. ? regular read latencies and ac timings apply. ? dll must be locked prior to mpr reads. note: * burst order bit 0 is assigned to lsb an d burst order bit 7 is assigned to msb of the selected mpr agent. a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 24 h5tq2g63bfr 1.10.3 mpr register address definition table 6 provides an overview of the available data loca tions, how they are addresse d by mr3 a[1:0] during a mrs to mr3, and how their individual bits are mapped into the burst order bits during a multi purpose regis- ter read. 1.10.4 relevant timing parameters the following ac timing parameters are important for operating the multi purpose register: trp, tmrd, tmod, and tmprr. for more details refer to ?electrical characteristics & ac timing for 800mhz? on page 71. 1.10.5 protocol example protocol example (this is one example): read out predetermined read-calibration pattern. description: multiple read s from multi purpose register, in order to do system level read timing calibration based on predetermined and standardized pattern. protocol steps: ? precharge all. ? wait until trp is satisfied. ? mrs mr3, opcode ?a2=1b? and ?a[1:0]=00b? ? redirect all subsequent reads into the multi purp ose register, and load pre-defined pattern into mpr. ? wait until tmrd and tmod are satisf ied (multi purpose register is t hen ready to be read). during the table 6. mpr mr3 register definition mr3 a[2] mr3 a[1:0] function burst length read address a[2:0] burst order and data pattern 1b 00b read predefined pattern for system calibration bl8 000b burst order 0,1,2,3,4,5,6,7 pre-defined data patt ern [0,1,0,1,0,1,0,1] bc4 000b burst order 0,1,2,3 pre-defined data pattern [0,1,0,1] bc4 100b burst order 4,5,6,7 pre-defined data pattern [0,1,0,1] 1b 01b rfu bl8 000b burst orde r 0,1,2,3,4,5,6,7 bc4 000b burst order 0,1,2,3 bc4 100b burst order 4,5,6,7 1b 10b rfu bl8 000b burst orde r 0,1,2,3,4,5,6,7 bc4 000b burst order 0,1,2,3 bc4 100b burst order 4,5,6,7 1b 11b rfu bl8 000b burst orde r 0,1,2,3,4,5,6,7 bc4 000b burst order 0,1,2,3 bc4 100b burst order 4,5,6,7 note: burst order bit 0 is assigned to lsb an d the burst order bit 7 is assigned to msb of the selected mpr agent. *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w z a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 25 h5tq2g63bfr ? period mr3 a2=1, no data write operation is allowed. ? read: ? a[1:0]=?00?b (data burst order is fixe d starting at nibble, always 00b here) ? a[2]=?0?b (for bl=8, burst orde r is fixed as 0,1,2,3,4,5,6,7) ? a12/bc=1 (use regular burst length of 8) ? all other address pins (including ba[2:0] and a10/ap): don?t care ? after rl=al+cl, dram bursts out the predefined read calibration pattern. ? memory controller repeats these calibration reads unt il read data capture at memory controller is opti- mized. ? after end of last mpr read burs t, wait until tmprr is satisfied. ? mrs mr3, opcode ?a2=0b? and ?a[1:0]=valid data but value are don?t care? ? all subsequent read and write accesses will be regular reads and writes from/to the dram array. ? wait until tmrd and tmod are satisfied. ? continue with ?regular? dram commands, like activate a memory bank for regular read or write access,... ? ? figure 11. mpr readout of predefined patter n, bl8 fixed burst order, single readout t0 ta tb0 tb1 tc0 tc1 tc2 tc3 tc4 tc5 tc6 nop mrs read nop nop nop nop nop nop tc7 tc8 tc9 td prea nop nop mrs write valid 3 valid 3 0 0 valid 1 0 0 00 valid 00 0 valid 1 0 0 valid 0 0 valid 0 0 valid 0 rl trp tmod tmprr tmod ck# ck cmd ba a[2] a10, ap a[11] a12, bc# a[15: 13] dqs, dqs# dq *1 *1 *1 notes: 1. rd with bl8 either by mrs or otf. 2. memory controller must drive 0 on a[2:0]. time break don ? t care *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w z a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 26 h5tq2g63bfr figure 12. mpr readout of predefined pattern, bl8 fixed burst order, back-to-back readout t0 ta tb tc0 tc1 tc2 tc3 tc4 tc5 tc6 tc7 nop mrs read read nop nop nop nop nop tc8 tc9 tc10 td prea mrs nop nop write valid 3 valid 3 0 0 2 valid 1 0 0 00 valid 00 0 valid 1 0 0 valid 0 0 valid 0 0 valid 0 rl trp tmod tmod ck# ck cmd ba a[1:0] a[2] a[9:3] a10, ap a[11] a12, bc# a[15: 13] dqs, dqs# dq *1 *1 *1 notes: 1. rd with bl8 either by mrs or otf. 2. memory controller must drive 0 on a[2:0]. time break don ? t care valid 2 0 2 0 valid valid valid valid valid rl tccd *1 tmprr *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w z a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 27 h5tq2g63bfr figure 13. mpr readout of predefined pattern, bc4, lower nibble then upper readout t0 ta tb tc0 tc1 tc2 tc3 tc4 tc5 tc6 tc7 nop mrs read read nop nop nop nop nop tc8 tc9 tc10 td prea nop nop mrs write valid 3 valid 3 0 0 valid 1 0 0 00 valid 00 0 valid 1 0 0 valid 0 0 valid 0 0 valid 0 rl trp tmod tmod ck# ck cmd ba a[1:0] a[2] a[9:3] a10, ap a[11] a12, bc# a[15: 13] dqs, dqs# dq *1 *2 *3 notes: 1. rd with bl8 either by mrs or otf. 2. memory controller must drive 0 on a[1:0]. 3. a[2]=0 selects lower 4 nibble bits 0...3. 4. a[2]=1 selects upper 4 nibble bits 4...7. time break don ? t care valid 2 0 1 valid valid valid valid valid rl tccd *1 tmprr *1 *1 *2 *4 *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w z a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 28 h5tq2g63bfr figure 14. mpr readout of predefined pattern, bc4, upper nibble then lower readout t0 ta tb tc0 tc1 tc2 tc3 tc4 tc5 tc6 tc7 nop mrs read read nop nop nop nop nop tc8 tc9 tc10 td prea nop nop mrs write valid 3 valid 3 0 0 valid 1 1 0 00 valid 00 0 valid 1 0 0 valid 0 0 valid 0 0 valid 0 rl trp tmod tmod ck# ck cmd ba a[1:0] a[2] a[9:3] a10, ap a[11] a12, bc# a[15: 13] dqs, dqs# dq *1 *2 *3 notes: 1. rd with bl8 either by mrs or otf. 2. memory controller must drive 0 on a[1:0]. 3. a[2]=0 selects lower 4 nibble bits 0...3. 4. a[2]=1 selects upper 4 nibble bits 4...7. time break don ? t care valid 2 0 0 valid valid valid valid valid rl tccd *1 tmprr *1 *1 *2 *4 *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w z a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 29 h5tq2g63bfr 2. command description 2.1 command truth table (a) note 1,2,3,4 apply to the entire command truth table (b) note 5 applies to all read/write command [ba = bank address, ra = rank address, ca = column address, bc = burst chop, x = don?t care, v = valid] function abbrev iation cke cs ras cas we ba0- ba3 a13- a15 a12- bc a10- ap a0- a9, a11 notes previ ous cycle curre nt cycle mode register set mrs h h l l l l ba op code refresh ref h h l l l h v v v v v self refresh entry sre h l l l l h v v v v v 7,9,12 self refresh exit srx l h hv vv vvv vv 7,8,9,1 2 lh hh single bank precharge pre h h l l h l ba v v l v precharge all banks prea h h l l h l v v v h v bank activate act h h l l h h ba row address (ra) write (fixed bl8 or bc4) wr h h l h l l ba rfu v l ca write (bc4, on the fly) wrs4 h h l h l l ba rfu l l ca write (bl8, on the fly) wrs8 h h l h l l ba rfu h l ca write with auto precharge (fixed bl8 or bc4) wra h h l h l l ba rfu v h ca write with auto precharge (bc4, on the fly) wras 4 hhlhllbarfulhca write with auto precharge (bl8, on the fly) wras 8 hhlhllbarfuhhca read (fixed bl8 or bc4) rd h h l h l h ba rfu v l ca read (bc4, on the fly) rds4 h h l h l h ba rfu l l ca read (bl8, on the fly) rds8 h h l h l h ba rfu h l ca read with auto precharge (fixed bl8 or bc4) rda h h l h l h ba rfu v h ca read with auto precharge (bc4, on the fly) rdas4 h h l h l h ba rfu l h ca read with auto precharge (bl8, on the fly) rdas8 h h l h l h ba rfu h h ca no operation nop h h l h h h v v v v v 10 device deselected des h h h x x x x x x x x 11 power down entry pde h l lh hh vvv vv6,12 hv vv *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w z a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 30 h5tq2g63bfr power down exit pdx l h lh hh vvv vv6,12 hv vv zq calibration long zqcl h h l h h l x x x h x zq calibration short zqcs h h l h h l x x x l x notes: 1. all ddr3 sdram commands are defined by states of cs , ras , cas , we and cke at the rising edge of the function abbrev iation cke cs ras cas we ba0- ba3 a13- a15 a12- bc a10- ap a0- a9, a11 notes previ ous cycle curre nt cycle *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w z a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 31 h5tq2g63bfr 2.2 cke truth table a) notes 1-7 apply to th e entire cke truth table. b) cke low is allowed only if tmrd and tmod are satisfied. current state 2 cke command (n) 3 ras , cas , we , cs action (n) 3 notes previous cycle 1 (n-1) current cycle 1 (n) power-down l l x maintain power-down 14, 15 l h deselect or nop power-down exit 11,14 self-refresh l l x maintain self-refresh 15,16 l h deselect or nop self-refresh exit 8,12,16 bank(s) active h l deselect or nop a ctive power-down entry 11,13,14 reading h l deselect or nop power-down entry 11,13,14,17 writing h l deselect or nop pow er-down entry 11,13,14,17 precharging h l deselect or nop p ower-down entry 11,13,14,17 refreshing h l deselect or nop p recharge power-down entry 11 all banks idle h l deselect or nop precharge power-down entry 11,13,14,18 h l refresh self-refresh 9,13,18 for more details with all signals see ?2.1 command truth table? on page 29.. 10 notes: 1. cke (n) is the logic state of cke at clock edge n; ck e (n-1) was the state of cke at the previous clock edge. 2. current state is defined as the state of th e ddr3 sdram immediately prior to clock edge n. 3. command (n) is the command registered at clock edge n, and action (n) is a result of command (n), odt is 18. ?idle state? is defined as all banks are closed (trp, tdal, et c. satisfied), no data bursts are in progress, cke is high, and all timings from previous operatio ns are satisfied (tmrd, tmod, trfc, tzqinit, tzqoper, tzqcs, etc . ) as well as a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 32 h5tq2g63bfr 3. absolute maximum ratings symbol parameter rating units notes vdd voltage on vdd pin relative to vss - 0.4 v ~ 1.975 v v ,3 vddq voltage on vddq pin relative to vss - 0.4 v ~ 1.975 v v ,3 vin, vout voltage on any pin relative to vss - 0.4 v ~ 1.975 v v tstg storage temperature -55 to +100 , 2 notes: a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 33 h5tq2g63bfr 4. operating conditions 4.1 operating temperature condition 4.2 recommended dc operating conditions symbol parameter rating units notes toper operating temperature (tcase) 0 to 85 o c 2 extended temperature range 85 to 95 o c1,3 notes: 1. operating temperature toper is the case surface temperature on the center / top side of the dram. o c and 95 o c case a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 34 h5tq2g63bfr 5. ac and dc inpu t measurement levels 5.1 ac and dc logic input leve ls for single-ended signals the dc-tolerance limits and ac -noise limits for the refere nce voltages vrefca and vrefdq are illustrated in below figure. it shows a valid reference voltage vref (t ) as a function of time. (vref stands for vrefca and vrefdq likewise). vref (dc) is the linear average of vref (t) over a very long period of time (e.g. 1 sec). this average has to meet the min/max requirements in table. furthermore vref (t) may temporarily deviate from vref (dc) by no more than +/- 1% vdd. illustration of vref (dc) to lerance and vref ac-noise limits single ended ac and dc input levels symbol parameter min max unit notes vih(dc) dc input logic high vref + 0.100 vdd v 1 vil(dc) dc input logic low vss vref - 0.100 v 1 vih(ac) ac input logic high vref + 0.175 - v 1, 2 vil(ac) ac input logic low vref - 0.175 v 1, 2 v refdq(dc) reference voltage for dq, dm inputs 0.49 * vdd 0.51 * vdd v 3, 4 v refca(dc) reference voltage for add, cmd inputs 0.49 * vdd 0.51 * vdd v 3, 4 notes: 1. for dq and dm, vref = vrefdq. for input any pins except reset , vref = vrefca. 2. the ?t.b.d.? entries might change based on overshoot and undershoot specification. 3. the ac peak noise on v ref may not allow v ref to deviate from v ref(dc) by more than +/-1% vdd vdd vss vdd/2 v ref(dc) v ref ac-noise voltage time v ref(dc)max v ref(dc)min v ref (t) *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w [ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 35 h5tq2g63bfr 5.2 ac and dc logic input leve ls for differential signals note1. refer to ?overshoot and undershoot specification on page 25? 5.3 differential inpu t cross point voltage to guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (ck, ck and dqs, dqs ) must meet the requirements below table. the differential input cross point voltage vi x is measured from the actual cross point of true and complement signal to the midlevel between of vdd and vss. vix definition cross point voltage for differ ential input signals (ck, dqs) symbol parameter min max unit notes vihdiff differential input logic high + 0.200 - v 1 vildiff differential input logic low - 0.200 v 1 symbol parameter min max unit notes v ix differential input cross point voltage relative to vdd/2 - 150 150 mv vdd vss vdd/2 v ix v ix v ix ck , dqs ck, dqs *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w [ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 36 h5tq2g63bfr 5.4 slew rate definitions fo r single ended input signals 5.4.1 input slew rate for input setup time (tis) and data setup time (tds) setup (tis and tds) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vref and the first crossing of vih (ac) min. setup (tis and tds) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vref and the first crossing of vil (ac) max. 5.4.2 input slew rate for input hold time (tih) and data hold time (tdh) hold nominal slew rate for a rising sign al is defined as the slew rate betw een the last crossing of vil (dc) max and the first crossing of vref. hold (tih and tdh) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vih ( dc) min and the first crossing of vref. single-ended input sl ew rate definition input nominal slew rate defi nition for single-ended signals description measured defined by applicable for min max input slew rate for rising edge vref vih (ac) min vih (ac) min-vref delta trs setup (tis, tds) input slew rate for falling edge vref vil (ac) max vref-vil (ac) max delta tfs input slew rate for rising edge vil (dc) max vref vref-vil (dc) max delta tfh hold (tih, tdh) input slew rate for falling edge vih (dc) min vref vih (dc) min-vref delta trh delta tfs delta trs vih(ac)m in vih (d c)m in vih (d c)m ax vih (ac)m ax vrefd q or vrefca part a: set up single ended input voltage(dq,add, cmd) part b: hold delta tfh delta trh vih (ac)m in vih(dc)m in vih (d c)m ax vih (ac)m ax vrefd q or vrefca single ended input voltage(dq,add, cmd) figure 82 f input nom inal slew rate definition for single -ended signals *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w [ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 37 h5tq2g63bfr 5.5 slew rate definitions fo r differential input signals input slew rate for differential signals (ck, ck and dqs, dqs ) are defined and measured as shown in ta b l e and figure . note: the differential signal (i.e. ck- ck and dqs- dqs ) must be linear between these thresholds. description measured defined by min max differential input slew rate for rising edge (ck- ck and dqs- dqs ) vildiffmax vihdiffmin vihdiffmin-vildiffmax deltatrdiff differential input slew rate for falling edge (ck- ck and dqs- dqs ) vihdiffmin vildiffmax vihdiffmin-vildiffmax deltatfdiff delta tfdiff delta trdiff vihdiffmin vildiffmax 0 differential input voltag e (i.e. dqs-dqs; ck-ck) differential input slew rate definition for dqs, dqs# and ck, ck# *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w [ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 38 h5tq2g63bfr 6. ac and dc output measurement levels 6.1 single ended ac and dc output levels ta b l e shows the output levels used for measurements of single ended signals. 6.1.1 differential ac and dc output levels below table shows the output levels used for measurements of differential signals. 6.2 single ended output slew rate with the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between vol(ac) and voh(ac) for single ended signals as shown in ta b l e and figure. note: output slew rate is verified by design and characte risation, and may not be subject to production test. symbol parameter 800/900mhz & 1.0ghz unit notes voh(dc) dc output high measurement level (for iv curve linearity) 0.8 x vddq v vom(dc) dc output mid measurement level (for iv curve linearity) 0.5 x vddq v vol(dc) dc output low measurement le vel (for iv curve linearity) 0.2 x vddq v voh(ac) ac output high measurement level (for output sr) vtt + 0.1 x vddq v 1 vol(ac) ac output low measurement level (for output sr) vtt - 0.1 x vddq v 1 1. the swing of 0. ? ? 0.2 ? ? description measured defined by from to single ended output slew rate for rising edge vol(ac) voh(ac) voh(ac)-vol(ac) deltatrse single ended output slew rate for falling edge voh(ac) vol(ac) voh(ac)-vol(ac) deltatfse *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w [ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 39 h5tq2g63bfr single ended output slew rate definition parameter symbol 800/900mhz & 1.0ghz units min max single-ended output slew rate srqse 2.5 5 v/ns delta tfse delta trse voh(ac) vol(ac) v ? single ended output voltage(l.e.dq) single ended output slew rate definition output slew rate (single-ended) *** for ron = rzq/7 setting *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w [ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 40 h5tq2g63bfr 6.3 differential output slew rate with the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between voldiff (ac) and vohdiff (ac) for differential signals as shown in ta b l e and figure . differential output slew rate definition note: output slew rate is verified by design and characte rization, and may not be subject to production test. differential output slew rate definition differential output slew rate ***for ron = rzq/7 setting description measured defined by from to differential output slew rate for rising edge voldiff (ac) vohdiff (ac) vohdiff (ac)-voldiff (ac) deltatrdiff differential output slew rate for falling edge vohdiff (ac) voldiff (ac) vohdiff (ac)-voldiff (ac) deltatfdiff parameter symbol 800/900mhz & 1.0ghz units min max differential output slew rate srqdiff 5 10 v/ns delta tfdiff delta trdiff vohdiff(ac) voldiff(ac) o differential output voltage(i.e. dqs-dqs) differential output slew rate definition *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w [ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 41 h5tq2g63bfr 6.4 reference load for ac ti ming and output slew rate figure represents the effective reference load of 25 ohms used in defining the relevant ac timing parameters of the device as well as output slew rate measurements. it is not intended as a precise representation of any particul ar system environment or a depiction of the actual load pre- sented by a production tester. system desi gners should use ibis or ot her simulation tools to correlate the timing reference load to a system environment. manufactur ers correlate to their production test co nditions, generally one or more coaxial transmission lines terminated at the tester electronics. dut dq dqs dqs vddq 25 ohm vtt = vddq/2 ck, ck reference load for ac timing and output slew rate *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w [ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 42 h5tq2g63bfr 7. overshoot and undershoot specifications 7.1 address and control overshoot and undershoot specifications ac overshoot/undershoot specific ation for address and control pins description specification 800mhz 900mhz 1.0ghz maximum peak amplitude allowed for overshoot area (see figure) 0.4v 0.4v 0.4v maximum peak amplitude allowed for undershoot area (see figure) 0.4v 0.4v 0.4v maximum overshoot area above vdd (see figure) 0.33 v-ns 0.28 v-ns 0.27 v-ns maximum undershoot area below vss (see figure) 0.33 v-ns 0.28 v-ns 0.27 v-ns m axim um am plitude overshoot area vdd vss maximum amplitude undershoot area time (ns) address and control overshoot and undershoot definition *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w [ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 43 h5tq2g63bfr 7.2 clock, data, strobe and mask overshoot and un dershoot specifications ac overshoot/undershoot specificatio n for clock, data, strobe and mask description specification 800mhz 900mhz 1.0ghz maximum peak amplitude allowed for overshoot area (see figure) 0.4v 0.4v 0.4v maximum peak amplitude allowed for undershoot area (see figure) 0.4v 0.4v 0.4v maximum overshoot area above vddq (see figure) 0.13 v-ns 0.11 v-ns 0.10 v-ns maximum undershoot area below vssq (see figure) 0.13 v-ns 0.11 v-ns 0.10 v-ns m axim um am plitude overshoot area vddq vssq maximum amplitude undershoot area time (ns) clock, data strobe and mask overshoot and undershoot definition volts (v) *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w [ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 44 h5tq2g63bfr 7.3 34 ohm output driver dc electrical characteristics a functional representation of the output buffer is shown in figure . output driver impedance ron is defined by the value of the external reference resistor rzq as follows: ron34 = rzq / 7 (nominal 34.3 w 10% with nominal rzq = 240 w 1%) the individual pull-up and pull-down resistor s (ronpu and ronpd) are defined as follows: under the condition that ronpd is turned off under the condition that ronpu is turned off ron pu v ddq v out ? i out -------------------- ------------------ = ron pd v out i out -------------- - = to other circuitry like rcv, ... ipu ronpu ronpd ipd output driver iout vout vssq dq vddq chip in drive mode output driver: definition of voltages and currents *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w [ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 45 h5tq2g63bfr notes: 1. the tolerance limits are specified af ter calibration with stable voltage and temperature. for the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity. 2. the tolerance limits are specif ied under the condition that vddq = vdd and that vssq = vss. 3. pull-down and pull-up output driver impedances are recommended to be calibrated at 0.5 x vddq. other calibration schemes may be used to achieve the linea rity spec shown above, e.g. calibration at 0.2 x vddq and 0.8 x vddq. 4. measurement definition for mismatch between pull-up and pull-down, mmpupd: measure ronpu and ronpd, both at 0.5 x vddq: if temperature and/or voltage change after calibr ation, the tolerance limits widen according to ta b l e and ta b l e . dt = t - t (@calibration); dv= vddq - vddq (@calibration); vdd = vddq drondt and drondv are not subject to production te st but are verified by design and characterization. output driver dc electrical characteristics, assuming r zq = 240 ; entire operating temperature range; after proper zq calibration ron nom resistor v out min nom max unit notes 34 ron 34pd v oldc = 0.2 v ddq 0.6 1.0 1.1 r zq /7 1, 2, 3 v omdc = 0.5 v ddq 0.9 1.0 1.1 r zq /7 1, 2, 3 v ohdc = 0.8 v ddq 0.9 1.0 1.4 r zq /7 1, 2, 3 ron 34pu v oldc = 0.2 v ddq 0.9 1.0 1.4 r zq /7 1, 2, 3 v omdc = 0.5 v ddq 0.9 1.0 1.1 r zq /7 1, 2, 3 v ohdc = 0.8 v ddq 0.6 1.0 1.1 r zq /7 1, 2, 3 mismatch between pull-up and pull-down, mm pupd v omdc 0.5 v ddq -10 +10 % 1, 2, 4 output driver sensitivity definition min max unit ronpu@ v ohdc 0.6 - dr on dth*| t| - dr on dvh*| v| 1.1 + dr on dth*| t| + dr on dvh*| v| rzq/7 ron@ v omdc 0.9 - dr on dtm*| t| - dr on dvm*| v| 1.1 + dr on dtm*| t| + dr on dvm*| v| rzq/7 ronpd@ v oldc 0.6 - dr on dtl*| t| - dr on dvl*| v| 1.1 + dr on dtl*| t| + dr on dvl*| v| rzq/7 output driver voltage an d temperature sensitivity min max unit dr on dtm 0 1.5 %/ o c dr on dvm 0 0.15 %/mv dr on dtl 0 1.5 %/ o c dr on dvl 0 tbd %/mv mm pupd ron pu ron pd ? ron nom ---------------- ----------------- ---------------- x 100 = *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w [ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 46 h5tq2g63bfr these parameters may not be subject to production te st. they are verified by design and characterization. 7.5 on-die termination (odt) levels and i-v characteristics 7.5.1 on-die termination (odt) levels and i-v characteristics on-die termination effective resistance rtt is defined by bits a9, a6 and a2 of the mr1 register. odt is applied to the dq, dm, dqs/dqs and tdqs/tdqs (x8 devices only) pins. a functional representation of the on-die termination is shown in figure . the in dividual pull-up and pull-down resistors (rttpu and rttpd) are defined as follows: under the condition that rttpd is turned off under the condition that rttpu is turned off dr on dth 0 1.5 %/ o c dr on dvh 0 tbd %/mv output driver voltage an d temperature sensitivity min max unit rtt pu v ddq v out ? i out ------------------- -------------- = rtt pd v out i out ------------ - = to other circuitry like rcv, ... ipu rttpu rttpd ipd odt iout vout vssq dq vddq c h ip in t e rm in a tio n m o d e o n-d ie term ination : d efinition of voltages and currents iout = ipd-ipu io_ctt_definition_01 *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w [ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 47 h5tq2g63bfr 7.5.2 odt dc electrical characteristics a below table provides an overview of the odt dc electrical characteristics. the values for rtt60pd120, rtt60pu120, rtt120pd240, rtt120pu240, rtt40pd80, rt t40pu80, rtt30pd60, rtt30pu60, rt t20pd40, rtt20pu40 are not specifi- cation requirements, but can be used as design guide lines: odt dc electrical characteristics, assuming r zq = 240 +/- 1% entire operating temperature range; after proper zq calibration mr1 a9, a6, a2 rtt resistor v out min nom max unit notes 0, 1, 0 120 rtt 120pd240 v oldc 0.2 v ddq 0.6 1.00 1.1 r zq 1) 2) 3) 4) 0.5 v ddq 0.9 1.00 1.1 r zq 1) 2) 3) 4) v ohdc 0.8 v ddq 0.9 1.00 1.4 r zq 1) 2) 3) 4) rtt 120pu240 v oldc 0.2 v ddq 0.9 1.00 1.4 r zq 1) 2) 3) 4) 0.5 v ddq 0.9 1.00 1.1 r zq 1) 2) 3) 4) v ohdc 0.8 v ddq 0.6 1.00 1.1 r zq 1) 2) 3) 4) rtt 120 v il(ac) to v ih(ac) 0.9 1.00 1.6 r zq /2 1) 2) 5) 0, 0, 1 60 rtt 60pd120 v oldc 0.2 v ddq 0.6 1.00 1.1 r zq /2 1) 2) 3) 4) 0.5 v ddq 0.9 1.00 1.1 r zq /2 1) 2) 3) 4) v ohdc 0.8 v ddq 0.9 1.00 1.4 r zq /2 1) 2) 3) 4) rtt 60pu120 v oldc 0.2 v ddq 0.9 1.00 1.4 r zq /2 1) 2) 3) 4) 0.5 v ddq 0.9 1.00 1.1 r zq /2 1) 2) 3) 4) v ohdc 0.8 v ddq 0.6 1.00 1.1 r zq /2 1) 2) 3) 4) rtt 60 v il(ac) to v ih(ac) 0.9 1.00 1.6 r zq /4 1) 2) 5) *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w [ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 48 h5tq2g63bfr the tolerance limits are specified after calibration with stable voltage and temperature. for the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity. the tolerance limits are specified under the co ndition that vddq = vdd and that vssq = vss. pull-down and pull-up odt resistors are recommended to be ca librated at 0.5 x vddq. other calibration schemes may be used to achieve the linearity spec shown above, e.g. calibration at 0.2 x vddq and 0.8 x vddq. not a specification requiremen t, but a design guide line. measurement definition for rtt: 0, 1, 1 40 rtt 40pd80 v oldc 0.2 v ddq 0.6 1.00 1.1 r zq /3 1) 2) 3) 4) 0.5 v ddq 0.9 1.00 1.1 r zq /3 1) 2) 3) 4) v ohdc 0.8 v ddq 0.9 1.00 1.4 r zq /3 1) 2) 3) 4) rtt 40pu80 v oldc 0.2 v ddq 0.9 1.00 1.4 r zq /3 1) 2) 3) 4) 0.5 v ddq 0.9 1.00 1.1 r zq /3 1) 2) 3) 4) v ohdc 0.8 v ddq 0.6 1.00 1.1 r zq /3 1) 2) 3) 4) rtt 40 v il(ac) to v ih(ac) 0.9 1.00 1.6 r zq /6 1) 2) 5) 1, 0, 1 30 rtt 30pd60 v oldc 0.2 v ddq 0.6 1.00 1.1 r zq /4 1) 2) 3) 4) 0.5 v ddq 0.9 1.00 1.1 r zq /4 1) 2) 3) 4) v ohdc 0.8 v ddq 0.9 1.00 1.4 r zq /4 1) 2) 3) 4) rtt 30pu60 v oldc 0.2 v ddq 0.9 1.00 1.4 r zq /4 1) 2) 3) 4) 0.5 v ddq 0.9 1.00 1.1 r zq /4 1) 2) 3) 4) v ohdc 0.8 v ddq 0.6 1.00 1.1 r zq /4 1) 2) 3) 4) rtt 30 v il(ac) to v ih(ac) 0.9 1.00 1.6 r zq /8 1) 2) 5) 1, 0, 0 20 rtt 20pd40 v oldc 0.2 v ddq 0.6 1.00 1.1 r zq /6 1) 2) 3) 4) 0.5 v ddq 0.9 1.00 1.1 r zq /6 1) 2) 3) 4) v ohdc 0.8 v ddq 0.9 1.00 1.4 r zq /6 1) 2) 3) 4) rtt 20pu40 v oldc 0.2 v ddq 0.9 1.00 1.4 r zq /6 1) 2) 3) 4) 0.5 v ddq 0.9 1.00 1.1 r zq /6 1) 2) 3) 4) v ohdc 0.8 v ddq 0.6 1.00 1.1 r zq /6 1) 2) 3) 4) rtt 20 v il(ac) to v ih(ac) 0.9 1.00 1.6 r zq /12 1) 2) 5) deviation of v m w.r.t. v ddq /2, d v m -5 +5 % 1) 2) 5) 6) odt dc electrical characteristics, assuming r zq = 240 +/- 1% entire operating temperature range; after proper zq calibration mr1 a9, a6, a2 rtt resistor v out min nom max unit notes *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w [ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 49 h5tq2g63bfr apply vih (ac) to pin under test and measure current i(vih (a c)), then apply vil (ac) to pin under test and measure cur- rent i(vil (ac)) respectively. measurement definition for vm and dvm: these parameters may not be subject to production te st. they are verified by design and characterization odt sensitivity definition min max unit rtt 0.9 - dr tt dt*| t| - dr tt dv*| v| 1.6 + dr tt dt*| t| + dr tt dv*| v| rzq/2,4,6,8,12 odt voltage and temperature sensitivity min max unit dr tt dt 0 1.5 %/ o c dr tt dv 0 0.15 %/mv rtt v ih(ac) v il(ac) ? i (vih(ac)) i (vil(ac)) ? ---------------------------------- ----------------------- = v m 2 v m ? v ddq ----------------- -1 ? ?? ?? 100 ? = *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w [ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 50 h5tq2g63bfr 7.6 odt timing definitions 7.6.1 test load for odt timings different than for timing measurements, the refere nce load for odt timings is defined in figure . 7.6.2 odt timing reference load odt timing definitions definitions for taon, taonpd, taof, taofpd and tadc are pr ovided in the table and subs equent figures. measurement reference settings are provided in the table. odt timing definitions symbol begin point definition end point definition figure t aon rising edge of ck - ck defined by the end point of odtlon extrapolated poin t at vssq figure t aonpd rising edge of ck - ck with odt being first registered high extrapolated poin t at vssq figure t aof rising edge of ck - ck defined by the end point of odtloff end point: extrapolated point at vrtt_nom figure t aofpd rising edge of ck - ck with odt being first registered low end point: extrapolated point at vrtt_nom figure t adc rising edge of ck - ck defined by the end point of odtlcnw, odtlcwn4 or odtlcwn8 end point: extrapolated point at vrtt_wr and vrtt_nom respectively figure reference settings for odt timing measurements measured parameter rtt_nom setting rtt_wr setting v sw1 [v] v sw2 [v] note t aon r zq /4 na 0.05 0.10 r zq /12 na 0.10 0.20 t aonpd r zq /4 na 0.05 0.10 r zq /12 na 0.10 0.20 t aof r zq /4 na 0.05 0.10 r zq /12 na 0.10 0.20 t aofpd r zq /4 na 0.05 0.10 r zq /12 na 0.10 0.20 t adc r zq /12 r zq /2 0.20 0.30 bd_refload_odt ck ck, vddq dqs dqs, tdqs tdqs, dq, dm dut vtt = vssq rtt = 25 vssq timing reference points *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w [ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 51 h5tq2g63bfr definition of taon definition of taonpd ck ck vtt td_taon_def t aon vssq dqs dq, dm vssq dqs, tdqs tdqs, begin point: rising edge of ck - ck defined by the end point of odtlon v sw1 v sw2 end point: extrapolated point at vssq t sw1 t sw2 ck ck vtt td_taonpd_def t aonpd vssq dqs dq, dm vssq dqs, tdqs tdqs, begin point: rising edge of ck - ck with odt being first registered high v sw1 v sw2 end point: extrapolated point at vssq t sw1 t sw2 *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w [ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 52 h5tq2g63bfr definition of taof definition of taofpd ck ck vtt td_taof_def t aof dqs dq, dm dqs, tdqs tdqs, begin point: rising edge of ck - ck defined by the end point of odtloff end point: extrapolated point at vrtt_nom vrtt_nom vssq v sw1 v sw2 t sw1 t sw2 ck ck vtt td_taofpd_def t aofpd dqs dq, dm dqs, tdqs tdqs, begin point: rising edge of ck - ck with odt being first registered low end point: extrapolated point at vrtt_nom vrtt_nom vssq v sw1 v sw2 t sw1 t sw2 *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w [ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 53 h5tq2g63bfr definition of tadc ck ck td_tadc_def t adc dqs dq, dm dqs, tdqs tdqs, v sw1 v sw2 end point: extrapolated point at vrtt_nom t sw11 t sw21 t adc end point: extrapolated point at vrtt_wr vtt vssq vrtt_nom vrtt_wr vrtt_nom t sw12 t sw22 begin point: rising edge of ck - ck defined by the end point of odtlcnw begin point: rising edge of ck - ck defined by the end point of odtlcwn4 or odtlcwn8 *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w [ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 54 h5tq2g63bfr 8. idd and iddq spec ification parameters and test conditions 8.1 idd and iddq measurement conditions in this chapter, idd and iddq measurement conditions such as test load and patterns are defined. figure 1. shows the setup and test load for idd and iddq measurements. ? idd currents (such as idd0, idd1, idd2n, idd2nt, i dd2p0, idd2p1, idd2q, idd3n, idd3p, idd4r, idd4w, idd5b, idd6, idd6et, idd6tc and idd7) are measured as time-averaged curren ts with all vdd balls of the ddr3 sdram under test tied together. any iddq current is not included in idd currents. ? iddq currents (such as iddq2nt and iddq4r) are measured as time-averaged currents with all vddq balls of the ddr3 sdram under test tied together. any idd current is not included in iddq currents. attention: iddq values cannot be direct ly used to calculate io power of the ddr3 sdram. they can be used to sup- port correlation of simulated io power to actual io power as ou tlined in figure 2. in dra m module application, iddq cannot be measured separately since vdd and vddq are using one merged-power layer in module pcb. for idd and iddq measurements, the following definitions apply: ? ?0? and ?low? is defined as vin <= v ilac(max). ? ?1? and ?high? is defined as vin >= v ihac(max). ? ?floating? is defined as inputs are vref - vdd/2. ? timing used for idd and iddq measurement-loop patterns are provided in table 1 on page 39. ? basic idd and iddq measurement conditions are described in table 2 on page 42. ? detailed idd and iddq measurement-loop patterns are desc ribed in table 3 on page 42 through table 10 on page 47. ? idd measurements are done after properly initializing the ddr 3 sdram. this includes but is not limited to setting ron = rzq/7 (34 ohm in mr1); qoff = 0 b (output buffer enabled in mr1); rtt_nom = rzq/6 (4 0 ohm in mr1); rtt_wr = rzq/2 (120 ohm in mr2); tdqs feature disabled in mr1 ? attention: the idd and iddq measurement -loop patterns need to be executed at least one time before actual idd or iddq measurement is started. ? define d = {cs , ras , cas , we }:= {high, low, low, low} ?define d = {cs , ras , cas , we }:= {high, high, high, high} *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w [ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 55 h5tq2g63bfr figure 1 - measurement setup and test load for idd and iddq (optional) measurements [note: dimm level output test load co ndition may be different from above] figure 2 - correlation from simulated channel io power to actual channel io power supported by iddq measurement v dd ddr3 sdram v ddq reset ck/ck dqs, dqs cs ras , cas , we a, ba odt zq v ss v ssq dq, dm, tdqs, tdqs cke r tt = 25 ohm v ddq /2 i dd i ddq (optional) application specific memory channel environment channel io power simulation iddq simulation iddq simulation channel io power number iddq test load correction *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w [ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 56 h5tq2g63bfr table 1 -timings used for idd and iddq measurement-loop patterns table 2 -basic idd and iddq measurement conditions symbol 800mhz 900mhz 1.0ghz unit t ck 1.25 1.1 1.0 ns cl 10 11 12 nck n rcd 12 13 15 nck n rc 42 47 52 nck n ras 30 34 38 nck n rp 12 13 15 nck n faw x16 32 36 40 nck n rrd x16 6 6 6 nck n rfc - 2 gb 128 145 160 nck symbol description i dd0 operating one bank ac tive-precharge current cke: high; external clock: on; tck, nrc, nras, cl: see table 1 on page 39; bl: 8 a) ; al: 0; cs : high between act and pre; command, address, bank address inputs: partially toggling according to table 3 on page 42; data io: floating; dm: stable at 0; bank activity: cycling with one bank ac tive at a time: 0,0,1,1,2,2,... (see table 3 on page 42); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 3 on page 42 i dd1 operating one bank ac tive-precharge current cke: high; external clock: on; tck, nrc, nras, nrcd, cl: see table 1 on page 39; bl: 8 a) ; al: 0; cs : high between act, rd and pre; command, address; bank addr ess inputs, data io: partially toggling according to table 4 on page 43; dm: stable at 0; bank activity: cycl ing with on bank active at a time: 0,0,1,1,2,2,... (see table 4 on page 43); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 4 page 43 i dd2n precharge standby current cke: high; external clock: on; tck, cl: see table 1 on page 39; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggling acco rding to table 5 on page 44; data io: floating; dm: stable at 0; bank activity: all banks closed; outp ut buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 5 on page 44 *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w [ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 57 h5tq2g63bfr i dd2nt precharge standby odt current cke: high; external clock: on; tck, cl: see table 1 on page 39; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggling acco rding to table 6 on page 44; data io: floating; dm: stable at 0; bank activity: all banks closed; outp ut buffer and rtt: enabled in mode registers b) ; odt signal: toggling according to table 6 on page 44; pattern details: see table 6 on page 44 i ddq2nt (optional) precharge standby odt iddq current same definition like for idd2nt, however meas uring iddq current instead of idd current i dd2p0 precharge power-down current slow exit cke: low; external clock: on; tck, cl: see table 1 on page 39; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io : floating; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; precharge power down mode: slow exit c) i dd2p1 precharge power-down current fast exit cke: low; external clock: on; tck, cl: see table 1 on page 39; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io : floating; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; precharge power down mode: fast exit c) i dd2q precharge quiet standby current cke: high; external clock: on; tck, cl: see table 1 on page 39; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: floating; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0 i dd3n active standby current cke: high; external clock: on; tck, cl: see table 1 on page 39; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggling acco rding to table 5 on page 44; data io: floating; dm: stable at 0; bank activity: all banks open; out put buffer and rtt: e nabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 5 on page 44 i dd3p active power-down current cke: low; external clock: on; tck, cl: see table 1 on page 39; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: floa ting; dm: stable at 0; bank activity: all banks open; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0 i ddq4r (optional) operating burst read iddq current same definition like for idd4r, however meas uring iddq current instead of idd current *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w [ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 58 h5tq2g63bfr i dd4r operating burst read current cke: high; external clock: on; tck, cl: see table 1 on page 39; bl: 8 a) ; al: 0; cs : high between rd; com- mand, address, bank address inputs: partially toggli ng according to table 7 on page 45; data io: seamless read data burst with different data bet ween one burst and the next one according to table 7 on page 45; dm: stable at 0; bank activity: all banks open, rd command s cycling through banks: 0,0, 1,1,2,2,...(see table 7 on page 45); output buffer and rt t: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 7 on page 45 i dd4w operating burst write current cke: high; external clock: on; tck, cl: see table 1 on page 39; bl: 8 a) ; al: 0; cs : high between wr; com- mand, address, bank address inputs: partially toggli ng according to table 8 on page 45; data io: seamless read data burst with different data bet ween one burst and the next one according to table 8 on page 45; dm: stable at 0; bank activity: all banks open, wr comma nds cycling through banks: 0,0,1,1,2,2,...(see table 8 on page 45); output buffer and rt t: enabled in mode registers b) ; odt signal: stable at high; pattern details: see table 8 on page 45 i dd5b burst refresh current cke: high; external clock: on; tck, cl, nrfc: see table 1 on page 38; bl: 8 a) ; al: 0; cs : high between ref; command, address, bank address inputs: partially togg ling according to table 9 on page 45; data io: float- ing; dm: stable at 0; bank activity: ref command ev ery nref (see table 9 on page 45); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 9 on page 45 i dd6 self-refresh current: normal temperature range t case : 0 - 85 o c; auto self-refre sh (asr): disabled d) ;self-refresh temperature range (srt): normal e) ; cke: low; external clock: off; ck and ck : low; cl: see table 1 on page 4; bl: 8 a) ; al: 0; cs , command, address, bank address inputs, data io: floating; dm: stable at 0; bank activity: self-refresh operation; output buffer and rtt: enabled in mode registers b) ; odt signal: floating i dd6et self-refresh current: extended temperature range (optional) f) t case : 0 - 95 o c; auto self-refre sh (asr): disabled d) ;self-refresh temperature range (srt): extended e) ; cke: low; external clock: off; ck and ck : low; cl: see table 1 on page 4; bl: 8 a) ; al: 0; cs , command, address, bank address inputs, data io: floating; dm : stable at 0; bank acti vity: extended temperature self-refresh operation; output buffer and rtt: enabled in mode registers b) ; odt signal: floating i dd6tc auto self-refresh current (optional) f) t case : 0 - 95 o c; auto self-refre sh (asr): enabled d) ;self-refresh temperature range (srt): normal e) ; cke: low; external clock: off; ck and ck : low; cl: see table 1 on page 39; bl: 8 a) ; al: 0; cs , command, address, bank address inputs, data io: floating; dm: stable at 0; bank activity: auto self-refresh opera- tion; output buffer and rtt: enabled in mode registers b) ; odt signal: floating *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w [ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 59 h5tq2g63bfr a) burst length: bl8 fixed by mrs: set mr0 a[1,0]=00b b) output buffer enable: set mr1 a[12] = 0b; set mr1 a[ 5,1] = 01b; rtt_nom enable: set mr1 a[9,6,2] = 011b; rtt_wr enable: set mr2 a[10,9] = 10b c) precharge power down mode: set mr0 a12=0b for slow exit or mr0 a12 = 1b for fast exit d) auto self-refresh (asr): set mr2 a6 = 0b to disable or 1b to enable feature e) self-refresh temperature range (srt): set mr2 a7 = 0b for normal or 1b for extended temperature range f) refer to dram supplier data sheet and/ or dimm spd to determine if optional fe atures or requirements are supported by ddr3 sdram device table 3 - idd0 measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are floating. b) dq signals are floating. i dd7 operating bank interleave read current cke: high; external clock: on; tck, nrc, nras, nrcd, nrrd, nfaw, cl: see table 1 on page 39; bl: 8 a) ; al: cl-1; cs : high between act and rda; command, address, bank address inputs: partially toggling according to table 10 on page 47; data io: read data burst with different data between one burst and the next one according to table 10 on page 47; dm: stable at 0; bank activity: two times interleaved cycling through banks (0, 1,...7) with different addressing, wee table 10 on page 47; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 10 on page 47 ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 act 0 0 1 1 0 0 00 0 0 0 0 - 1,2 d, d 1 0 0 0 0 0 00 0 0 0 0 - 3,4 d , d 1111 0 0000 0 0 0 - ... repeat pattern 1...4 until nras - 1, truncate if necessary nras pre 0 0 1 0 0 0 00 0 0 0 0 - ... repeat pattern 1...4 until nrc - 1, truncate if necessary 1*nrc+0 act 0 0 1 1 0 00 00 0 0 f 0 - ... repeat pattern 1...4 until 1*nrc + nras - 1, truncate if necessary 1*nrc+nras pre 0 0 1 0 0 0 00 0 0 f 0 - ... repeat pattern 1...4 until 2*nrc - 1, truncate if necessary 1 2*nrc repeat sub-loop 0, use ba[2:0] = 1 instead 2 4*nrc repeat sub-loop 0, use ba[2:0] = 2 instead 3 6*nrc repeat sub-loop 0, use ba[2:0] = 3 instead 4 8*nrc repeat sub-loop 0, use ba[2:0] = 4 instead 5 10*nrc repeat sub-loop 0, use ba[2:0] = 5 instead 6 12*nrc repeat sub-loop 0, use ba[2:0] = 6 instead 7 14*nrc repeat sub-loop 0, use ba[2:0] = 7 instead *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w [ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 60 h5tq2g63bfr table 4 - idd1 measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are used according to rd commands, otherwise floating. b) burst sequence driven on each dq signal by read command. outside burst operation, dq signals are floating. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 act001100000000 - 1,2 d, d 1 0 0 0 0 0 00 0 0 0 0 - 3,4 d , d 111100000000 - ... repeat pattern 1...4 until nrcd - 1, truncate if necessary nrcd rd 0 1 0 1 0 0 00 0 0 0 0 00000000 ... repeat pattern 1...4 until nras - 1, truncate if necessary nras pre 0 0 1 0 0 0 00 0 0 0 0 - ... repeat pattern 1...4 until nrc - 1, truncate if necessary 1*nrc+0 act 0 0 1 1 0 0 00 0 0 f 0 - 1*nrc+1,2 d, d 1 0 0 0 0 0 00 0 0 f 0 - 1*nrc+3,4 d , d 1111000000f0 - ... repeat pattern nrc + 1,...4 until n rc + nrce - 1, truncate if necessary 1*nrc+nrcd rd 0 1 0 1 0 0 00 0 0 f 0 00110011 ... repeat pattern nrc + 1,...4 until nrc + nras - 1, truncate if necessary 1*nrc+nras pre 0 0 1 0 0 0 00 0 0 f 0 - ... repeat pattern nrc + 1,...4 until *2 nrc - 1, trun cate if necessary 1 2*nrc repeat sub-loop 0, use ba[2:0] = 1 instead 2 4*nrc repeat sub-loop 0, use ba[2:0] = 2 instead 3 6*nrc repeat sub-loop 0, use ba[2:0] = 3 instead 4 8*nrc repeat sub-loop 0, use ba[2:0] = 4 instead 5 10*nrc repeat sub-loop 0, use ba[2:0] = 5 instead 6 12*nrc repeat sub-loop 0, use ba[2:0] = 6 instead 7 14*nrc repeat sub-loop 0, use ba[2:0] = 7 instead *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w [ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 61 h5tq2g63bfr table 5 - idd2n and idd3n measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are floating. b) dq signals are floating. table 6 - idd2nt and iddq2nt measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are floating. b) dq signals are floating. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 d10000000000 - 1d10000000000- 2d 111 1 0 0 0 0 0 f0 - 3d 111 1 0 0 0 0 0 f0 - 1 4-7 repeat sub-loop 0, use ba[2:0] = 1 instead 2 8-11 repeat sub-loop 0, use ba[2:0] = 2 instead 3 12-15 repeat sub-loop 0, use ba[2:0] = 3 instead 4 16-19 repeat sub-loop 0, use ba[2:0] = 4 instead 5 20-23 repeat sub-loop 0, use ba[2:0] = 5 instead 6 24-17 repeat sub-loop 0, use ba[2:0] = 6 instead 7 28-31 repeat sub-loop 0, use ba[2:0] = 7 instead ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 d10000000000 - 1d10000000000- 2d 1111 0 0 0 0 0 f 0 - 3d 1 1 1 1 0 0 0 0 0 f 0 00000000 1 4-7 repeat sub-loop 0, but odt = 0 and ba[2:0] = 1 2 8-11 repeat sub-loop 0, but odt = 1 and ba[2:0] = 2 3 12-15 repeat sub-loop 0, but odt = 1 and ba[2:0] = 3 4 16-19 repeat sub-loop 0, but odt = 0 and ba[2:0] = 4 5 20-23 repeat sub-loop 0, but odt = 0 and ba[2:0] = 5 6 24-17 repeat sub-loop 0, but odt = 1 and ba[2:0] = 6 7 28-31 repeat sub-loop 0, but odt = 1 and ba[2:0] = 7 *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w \ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 62 h5tq2g63bfr table 7 - idd4r and iddq24rmeasurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are used according to rd commands, otherwise floating. b) burst sequence driven on each dq signal by read command. outside burst operation, dq signals are floating. table 8 - idd4w measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are used according to wr commands, otherwise floating. b) burst sequence driven on each dq signal by write command. outside burst operation, dq signals are floating. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 rd 0 1 0 1 0 0 00 0 0 0 0 00000000 1d100000000000- 2,3 d ,d 1111 0 0000 0 0 0 - 4 rd 0 1 0 1 0 0 00 0 0 f 0 00110011 5d1000000000f0- 6,7 d ,d 1111 0 0000 0 f 0 - 1 8-15 repeat sub-loop 0, but ba[2:0] = 1 2 16-23 repeat sub-loop 0, but ba[2:0] = 2 3 24-31 repeat sub-loop 0, but ba[2:0] = 3 4 32-39 repeat sub-loop 0, but ba[2:0] = 4 5 40-47 repeat sub-loop 0, but ba[2:0] = 5 6 48-55 repeat sub-loop 0, but ba[2:0] = 6 7 56-63 repeat sub-loop 0, but ba[2:0] = 7 ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 wr 0 1 0 0 1 0 00 0 0 0 0 00000000 1d100010000000- 2,3 d ,d 1111 1 0000 0 0 0 - 4 wr 0 1 0 0 1 0 00 0 0 f 0 00110011 5d1000100000f0- 6,7 d ,d 1111 1 0000 0 f 0 - 1 8-15 repeat sub-loop 0, but ba[2:0] = 1 2 16-23 repeat sub-loop 0, but ba[2:0] = 2 3 24-31 repeat sub-loop 0, but ba[2:0] = 3 4 32-39 repeat sub-loop 0, but ba[2:0] = 4 5 40-47 repeat sub-loop 0, but ba[2:0] = 5 6 48-55 repeat sub-loop 0, but ba[2:0] = 6 7 56-63 repeat sub-loop 0, but ba[2:0] = 7 *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w \ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 63 h5tq2g63bfr table 9 - idd5b measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are floating. b) dq signals are floating. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 ref 0 0 0 1 0 0 0 0 0 0 0 - 1 1.2 d, d 1 0 0 0 0 0 00 0 0 0 0 - 3,4 d , d 1111 0 0000 0 f 0 - 5...8 repeat cycles 1...4, but ba[2:0] = 1 9...12 repeat cycles 1...4, but ba[2:0] = 2 13...16 repeat cycles 1...4, but ba[2:0] = 3 17...20 repeat cycles 1...4, but ba[2:0] = 4 21...24 repeat cycles 1...4, but ba[2:0] = 5 25...28 repeat cycles 1...4, but ba[2:0] = 6 29...32 repeat cycles 1...4, but ba[2:0] = 7 2 33...nrfc-1 repeat sub-loop 1, until nrfc - 1. truncate, if necessary. *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w \ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 64 h5tq2g63bfr table 10 - idd7 measurement-loop pattern a) attention! sub-loops 10-19 have inverse a[6:3] pattern and data pattern than sub-loops 0-9 a) dm must be driven low all the time. dqs, dqs are used according to rd commands, otherwise floating. b) burst sequence driven on each dq signal by read command. outside burst operation, dq signals are floating. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 act 0 0 1 1 0 0 00 0 0 0 0 - 1 rda 0 1 0 1 0 0 00 1 0 0 0 00000000 2d100000000000- ... repeat above d command until nrrd - 1 1 nrrd act 0 0 1 1 0 1 00 0 0 f 0 - nrrd+1 rda 0 1 0 1 0 1 00 1 0 f 0 00110011 nrrd+2 d 1 0 0 0 0 1 00 0 0 f 0 - ... repeat above d command until 2* nrrd - 1 2 2*nrrd repeat sub-loop 0, but ba[2:0] = 2 3 3*nrrd repeat sub-loop 1, but ba[2:0] = 3 4 4*nrrd ... d1000030000f0 - assert and repeat above d command until nfaw - 1, if necessary 5 nfaw repeat sub-loop 0, but ba[2:0] = 4 6 nfaw+nrrd repeat sub-loop 1, but ba[2:0] = 5 7 nfaw+2*nrrd repeat sub-lo op 0, but ba[2:0] = 6 8 nfaw+3*nrrd repeat sub-lo op 1, but ba[2:0] = 7 9 nfaw+4*nrrd ... d1000070000f0 - assert and repeat above d command until 2* nfaw - 1, if necessary 10 2*nfaw+0 act 0 0 1 1 0 0 00 0 0 f 0 - 2*nfaw+1 rda 0 1 0 1 0 0 00 1 0 f 0 00110011 2&nfaw+2 d1000000000f0 - repeat above d command until 2* nfaw + nrrd - 1 11 2*nfaw+nrrd act 0 0 1 1 0 1 00 0 0 0 0 - 2*nfaw+nrrd+1 rda 0 1 0 1 0 1 00 1 0 0 0 00000000 2&nfaw+nrrd+2 d100001000000 - repeat above d command until 2* nfaw + 2* nrrd - 1 12 2*nfaw+2*nrrd repeat sub-loop 10, but ba[2:0] = 2 13 2*nfaw+3*nrrd repeat sub-loop 11, but ba[2:0] = 3 14 2*nfaw+4*nrrd d100000000000 - assert and repeat above d command until 3* nfaw - 1, if necessary 15 3*nfaw repeat sub-loop 10, but ba[2:0] = 4 16 3*nfaw+nrrd repeat sub-loop 11, but ba[2:0] = 5 17 3*nfaw+2*nrrd repeat sub-loop 10, but ba[2:0] = 6 18 3*nfaw+3*nrrd repeat sub-loop 11, but ba[2:0] = 7 14 3*nfaw+4*nrrd d100000000000 - assert and repeat above d command until 4* nfaw - 1, if necessary *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w \ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 65 h5tq2g63bfr 8.2 idd specifications idd values are for full operating range of voltage and temperature unless otherwise noted. *idd values can be slightly c hanged when above table is updated. i dd specification speed grade bin 800mhz 900mhz 1.0ghz unit notes symbol max. max. max. i dd0 65 70 80 ma i dd1 80 85 95 ma i dd2n 30 35 40 ma i dd2p0 10 10 12 ma i dd2p1 20 20 22 ma i dd2q 30 35 40 ma i dd3n 42 45 50 ma i dd3p 20 22 25 ma i dd4r 155 170 185 ma i dd4w 165 180 200 ma i dd5 165 180 200 ma i dd6 10 10 12 ma i dd7 190 210 230 ma *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w \ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 66 h5tq2g63bfr 9. input/output capacitance 800mhz 900mhz 1.0ghz parameter symbol min max min max min max units notes input/output capacitance (dq, dm, dqs, dqs , tdqs, tdqs ) c io 1.5 2.3 tbd tbd tbd tbd pf 1,2,3 input capacitance, ck and ck c ck 0.8 1.4 tbd tbd tbd tbd pf 2,3 input capacitance delta ck and ck c dck 0 0.15 tbd tbd tbd tbd pf 2,3,4 input capacitance (all other input-only pins) c i 0.75 1.3 tbd tbd tbd tbd pf 2,3,6 input capacitance delta, dqs and dqs c ddqs 0 0.15 tbd tbd tbd tbd pf 2,3,5 input capacitance delta (all ctrl input-only pins) c di_ctrl -0.4 0.2 tbd tbd tbd tbd pf 2,3,7,8 input capacitance delta (all add/cmd input-only pins) c di_add_ cmd -0.4 0.4 tbd tbd tbd tbd pf 2,3,9,10 input/output capacitance delta (dq, dm, dqs, dqs ) c dio -0.5 0.3 tbd tbd tbd tbd pf 2,3,11 notes: 1. although the dm, tdqs and tdqs pins have different functions, the loading matches dq and dqs. 2. this parameter is not subject to prod uction test. it is verified by design and characterization. the capacitance is a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 67 h5tq2g63bfr 10. standard speed bins ddr3 sdram standard speed bins include tck, trcd, trp, tras and trc for each corresponding bin. 800mhz speed bins for specific notes see ?11. electrical ch aracteristics and ac timing? on page 71. speed bin 800mhz unit note parameter symbol min max internal read command to first data t aa 12.5 20 ns act to internal read or write delay time t rcd 15 ? ns pre command period t rp 15 ? ns act to act or ref command period t rc 51.25 ? ns act to pre command period t ras 37.5 9 * trefi ns cl = 5 cwl = 5 t ck(avg) 2.5 3.3 ns 1,2,3,4,6 cwl = 6, 7 t ck(avg) reserved ns 4 cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1,2,3,6 cwl = 6 t ck(avg) reserved ns 1,2,3,4,6 cwl = 7 t ck(avg) reserved ns 4 cl = 7 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 2.5 ns 1,2,3,4,6 cwl = 7 t ck(avg) reserved ns 1,2,3,4,6 cwl = 8 t ck(avg) reserved ns 4 cl = 8 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 2.5 ns 1,2,3,6 cwl = 7 t ck(avg) reserved ns 4 cl = 9 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 1.875 ns 1,2,3,4,6 cwl = 8 t ck(avg) reserved ns 4 cl = 10 cwl = 5,6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 1.875 ns 1,2,3,6 cwl = 8 t ck(avg) 1.25 1.5 ns 1,2,3,4 cl = 11 cwl = 5,6,7 t ck(avg) reserved ns 4 cwl = 8 t ck(avg) 1.25 1.5 ns 1,2,3,4 supported cl settings 5,6, 7,8, 9,10,11 n ck supported cwl settings 5, 6, 7,8 n ck *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w \ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 68 h5tq2g63bfr 900mhz speed bins for specific notes see ?11. electrical ch aracteristics and ac timing? on page 71. speed bin 900mhz unit note parameter symbol min max internal re ad command to first data t aa 13.2 20 ns act to internal read or write delay time t rcd 15.4 ? ns pre command period t rp 15.4 ? ns act to act or ref command period t rc 50.6 ? ns act to pre command period t ras 37.4 9 * trefi ns cl = 5 cwl = 5 t ck(avg) 2.5 3.3 ns 1,2,3,4,7 cwl = 6, 7 t ck(avg) reserved ns 4 cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1,2,3,7 cwl = 6 t ck(avg) reserved ns 1,2,3,4,7 cwl = 7 t ck(avg) reserved ns 4 cl = 7 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 2.5 ns 1,2,3,4,7 cwl = 7 t ck(avg) reserved ns 1,2,3,4,7 cwl = 8 t ck(avg) reserved ns 4 cl = 8 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 2.5 ns 1,2,3,7 cwl = 7 t ck(avg) reserved ns 1,2,3,4,7 cl = 9 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 1.875 ns 1,2,3,4,7 cwl = 8 t ck(avg) reserved ns 1,2,3,4 cl = 10 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 1.875 ns 1,2,3,7 cwl = 8 t ck(avg) 1.25 1.5 ns 1,2,3,4,7 cl = 11 cwl = 5, 6, 7 t ck(avg) reserved ns 4 cwl=8 t ck(avg) 1.25 1.5 1,2,3,4,7 cwl = 9 t ck(avg) 1.1 1.25 ns 1,2,3,4 supported cl settings 5,6, 7,8, 9,10,11 n ck supported cwl settings 5, 6, 7,8,9 n ck *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w \ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 69 h5tq2g63bfr 1.0ghzmhz speed bins for specific notes see ?11. electrical ch aracteristics and ac timing? on page 71. speed bin 1.0ghz unit note parameter symbol min max internal re ad command to first data t aa 12.0 20 ns act to internal read or write delay time t rcd 15 - ns pre command period t rp 15 - ns act to act or ref command period t rc 52 - ns act to pre command period t ras 37 9 * trefi ns cl = 5 cwl = 5 t ck(avg) 2.5 3.3 ns 1,2,3,4,8 cwl = 6, 7 t ck(avg) reserved ns 4 cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1,2,3,8 cwl = 6 t ck(avg) reserved ns 1,2,3,4,8 cwl = 7 t ck(avg) reserved ns 4 cl = 7 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 2.5 ns 1,2,3,4,8 cwl = 7 t ck(avg) reserved ns 1,2,3,4,8 cwl = 8 t ck(avg) reserved ns 4 cl = 8 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 2.5 ns 1,2,3,8 cwl = 7 t ck(avg) reserved ns 1,2,3,4,8 cl = 9 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 1.875 ns 1,2,3,4,8 cwl = 8 t ck(avg) reserved ns 1,2,3,4 cl = 10 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 1.875 ns 1,2,3,8 cwl = 8 t ck(avg) 1.25 1.5 ns 1,2,3,4 cl = 11 cwl = 5, 6, 7 t ck(avg) reserved ns 4 cwl = 8 t ck(avg) 1.25 1.5 ns 1,2,3,8 cwl = 9 t ck(avg) 1.0 1.25 ns 1,2,3,5 cl = 12 cwl = 5, 6, 7,8 t ck(avg) reserved ns 4 cwl = 9 t ck(avg) 1.0 1.25 ns 1,2,3,5,8 supported cl settings 5,6,7,8,9,10,11,12 n ck supported cwl settings 5,6,7,8,9 n ck *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w \ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 70 h5tq2g63bfr speed bin table notes absolute specification (t oper ; v ddq = v dd = 1.5v +/- 0.075 v); notes: 1. the cl setting and cwl sett ing result in tck(avg).min and tck(avg).max requirements. when ma king a selection of a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 71 h5tq2g63bfr 11. electrical characte ristics and ac timing timing parameters by speed bin note: the following general notes from page 61 apply to table : a 800mhz 900mhz 1.0ghz parameter symbol min max min max min max units notes clock timing minimum clock cycle time (dll off mode) tck (dll_off) 8-8-8-ns6 average clock period tck (avg) see ?10. standard speed bins? on page 62. ps f average high pulse width tch (avg)0.470.530.470.530.470.53 tck (avg) f average low pulse width tcl (avg) 0.47 0.53 0.47 0.53 0.47 0.53 tck (avg) f absolute clock period tck (abs) tck(avg)min+tjit(per)min ps absolute clock high pulse width tch (abs) 0.43 - 0.43 - 0.43 - tck (avg) 25 absolute clock low pulse width tcl (abs) 0.43 - 0.43 - 0.43 - tck (avg) 26 clock period jitter jit (per) -70 70 -60 60 -40 40 ps clock period jitter during dll locking period tjit (per, lck) -60 60 -50 50 -30 30 ps cycle to cycle period jitter tjit (cc) 140 140 130 130 tbd tbd ps cycle to cycle period jitter during dll locking period tjit (cc, lck) 120 120 110 110 tbd tbd ps duty cycle jitter tjit (duty) ----tbdtbdps cumulative error across 2 cycles terr (2per) -103 103 -93 93 tbd tbd ps cumulative error across 3 cycles terr (3per) -122 122 -112 112 tbd tbd ps cumulative error across 4 cycles terr (4per) -136 136 -122 122 tbd tbd ps cumulative error across 5 cycles terr (5per) -147 147 -135 135 tbd tbd ps cumulative error across 6 cycles terr (6per) -155 155 -140 140 tbd tbd ps cumulative error across 7 cycles terr (7per) -163 163 -146 146 tbd tbd ps cumulative error across 8 cycles terr (8per) -169 169 -149 149 tbd tbd ps cumulative error across 9 cycles terr (9per) -175 175 -160 160 tbd tbd ps cumulative error across 10 cycles terr (10per) -180 180 -165 165 tbd tbd ps *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w \ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 72 h5tq2g63bfr cumulative error across 11 cycles terr (11per) -184 184 -168 168 tbd tbd ps cumulative error across 12 cycles terr (12per) -188 188 -170 170 tbd tbd ps cumulative error across n = 13, 14,.....49, 50 cycles terr (nper) terr(nper)min=(1+0. 68ln(n))*jit(per)min terr(nper)max=(1+0.68ln(n))*jit(per)max ps 24 data timing dqs, dqs to dq skew, per group, per access tdqsq 100 - 87 - 75 - ps 13 dq output hold time from dqs, dqs tqh 0.38 - 0.38 - 0.38 - tck (avg) 13, b dq low-impedance time from ck, ck tlz (dq) -450 225 -400 200 -360 180 ps 13, 14, a dq high impedance time from ck, ck thz (dq) - 225 - 200 - 180 ps 13, 14, a data setup time to dqs, dqs referenced to vih (ac) / vil (ac) levels tds (base) 10 - 0 - -10 - ps d, 17 data hold time from dqs, dqs referenced to vih (dc) / vil (dc) levels tdh (base) 45 - 45 - 40 - ps d, 17 data strobe timing dqs,dqs differential read preamble trpre 0.9 note 0.9 note 0.9 tbd tck (avg) 13, 19 b dqs, dqs differential read postamble trpst 0.3 note 0.3 note 0.3 tbd tck (avg) 11, 13, b dqs, dqs differential output high time tqsh 0.38 - 0.38 - 0.38 - tck (avg) 13, b dqs, dqs differential output low time tqsl 0.38 - 0.38 - 0.38 - tck (avg) 13, b dqs, dqs differential write preamble twpre 0.9 - 0.9 - 0.9 - tck (avg) dqs, dqs differential write postamble twpst0.3-0.3-0.3- tck (avg) dqs, dqs rising edge output access time from rising ck, ck tdqsck -225 225 -180 180 -180 180 ps 13, a timing parameters by speed bin (continued) note: the following general notes from page 61 apply to table : a 800mhz 900mhz 1.0ghz parameter symbol min max min max min max units notes *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w \ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 73 h5tq2g63bfr dqs and dqs low- impedance time (referenced from rl - 1) tlz(dqs) -450 225 -400 200 -360 180 ps 13, 14, a dqs and dqs high- impedance time (referenced from rl + bl/2) thz(dqs) - 225 - 200 - 180 ps 13, 14 a dqs, dqs differential input low pulse width tdqsl 0.4 0.6 0.4 0.6 0.4 0.6 tck (avg) dqs, dqs differential input high pulse width tdqsh 0.4 0.6 0.4 0.6 0.4 0.6 tck (avg) dqs, dqs rising edge to ck, ck rising edge tdqss -0.25 0.25 -0.25 0.25 -0.3 0.3 tck (avg) c dqs, dqs falling edge setup time to ck, ck rising edge tdss0.2-0.2-0.2- tck (avg) c dqs, dqs falling edge hold time from ck, ck rising edge tdsh0.2-0.2-0.2- tck (avg) c command and address timing dll locking time tdllk 512 - 512 - 512 - nck internal read command to precharge command delay trtp max(4nck, 7.5ns) - max(4nck, 7.5ns) - max(4nck, 7.5ns) -e delay from start of internal write transaction to internal read command twtr max(4nck, 7.5ns) - max(4nck, 7.5ns) - max(4nck, 7.5ns) -e, 18 write recovery time twr 16.3 - 15.6 - 15 - ns e mode register set command cycle time tmrd4-4-4-nck mode register set command update delay tmod max(12nc k,15ns) - max(12nc k,15ns) - max(12nc k,15ns - act to internal read or write delay time trcd 16.3 - 15.6 - 15 - e pre command period trp 16.3 - 15.6 - 15 - e act to act or ref command period trc 52.5 - 50 - 51 - e cas to cas command delay tccd4-4-4-nck timing parameters by speed bin (continued) note: the following general notes from page 61 apply to table : a 800mhz 900mhz 1.0ghz parameter symbol min max min max min max units notes *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w \ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 74 h5tq2g63bfr auto precharge write recovery + precharge time tdal (min) 24 - 28 - 31 - nck end of mpr read burst to msr for mpr (exit) tmprr1-1-1-nck22 active to precharge command period tras 37.5 - 35.6 - 34 - e active to active command period for 2kb page size trrd7-7-7- e four activate window for 2kb page size tfaw 42.5 - 41.1 - 40 - ns e command and address setup time to ck, ck referenced to vih (ac) / vil (ac) levels tis (base) 45 - 35 25 - ps b, 16 command and address hold time from ck, ck referenced to vih (dc) / vil (dc) levels tih (base) 120 - 110 - 100 - ps b, 16 calibration timing - power-up and reset calibration time tzqinit 512 - 512 - 512 - nck normal operation full calibration time tzqoper 256 - 256 - 256 - nck normal operation short calibration time tzqcs64-64-64-nck23 reset timing exit reset from cke high to a valid command txpr max(5nsc k, trfc(min) +10ns) - max(5nsc k, trfc(min) +10ns) - max(5nsc k, trfc(min) +10ns) - self refresh timings exit self refresh to commands not requiring a locked dll txs max(5nsc k, trfc(min) +10ns) - max(5nsc k, trfc(min) +10ns) - max(5nsc k, trfc(min) +10ns) - exit self refresh to commands requiring a locked dll txsdll tdllk(min ) - tdllk(min ) - tdllk(min ) -nck minimum cke low width for self refresh entry to exit timing tckesr tcke(min)+1nck tcke(min)+1nck tcke(min) +1nck - timing parameters by speed bin (continued) note: the following general notes from page 61 apply to table : a 800mhz 900mhz 1.0ghz parameter symbol min max min max min max units notes *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w \ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 75 h5tq2g63bfr valid clock requirement after self refresh entry (sre) or power- down entry (pde) tcksre max(5nsc k, 10ns) - max(5nsc k, 10ns) - max(5nsc k, 10ns) - valid clock requirement before self refresh exit (srx) or power- down exit (pdx) or reset exit tcksrx max(5nsc k, 10ns) - max(5nsc k, 10ns) - max(5nsc k, 10ns) - power down timings exit power down with dll on to any valid command; exit precharge power down with dll frozen to commands not requiring a locked dll txp 7-7-7- exit precharge power down with dll frozen to commands requiring a locked dll txpdll max(10nc k,24ns) - max(10nc k,24ns) - max(10nc k,24ns) -2 cke minimum pulse width tcke4-5-5- command pass disable delay tcpded 1 - 1 - 1 - nck power down entry to exit timing tpd tcke(min) 9*trefi tcke(min) 9*trefi tcke(min) 9*trefi 15 timing of act command to power down entry tactpden 1 - 1 - 1 - nck timing of pre or prea command to power down entry tprpden 1 - 1 - 1 - nck timing of rd/rda command to power down entry trdpden rl+4+1 - rl+4+1 - rl+4+1 - nck timing of wr command to power down entry (bl8otf, bl8mrs, bc4otf) twrpden wl+4+(tw r/ tck(avg)) - wl+4+(tw r/ tck(avg)) - wl+4+(tw r/ tck(avg)) -nck9 timing parameters by speed bin (continued) note: the following general notes from page 61 apply to table : a 800mhz 900mhz 1.0ghz parameter symbol min max min max min max units notes *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w \ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 76 h5tq2g63bfr timing of wra command to power down entry (bl8otf, bl8mrs, bc4otf) twrapden wl+4+wr +1 - wl+4+wr +1 - wl+4+wr +1 -nck10 timing of wr command to power down entry (bc4mrs) twrpden wl+2+(tw r/ tck(avg)) - wl+2+(tw r/ tck(avg)) - wl+2+(tw r/ tck(avg)) -nck9 timing of wra command to power down entry (bc4mrs) twrapden wl+2+wr +1 - wl+2+wr +1 - wl+2+wr +1 -nck10 timing of ref command to power down entry trefpden 1 - 1 - 1 - nck , timing of mrs command to power down entry tmrspden tmod(min) - tmod(min) - tmod(min) - odt timings odt high time without write command or with write command and bc4 odth44-4-4-nck odt high time with write command and bl8 odth86-6-6-nck asynchronous rtt turn-on delay (power-down with dll frozen) taonpd191919ns asynchronous rtt turn-off delay (power- down with dll fro- zen) taofpd191919ns rtt turn-on taon -225 225 -200 200 -175 175 ps 7, a rtt_nom and rtt_wr turn-off time from odtloff reference taof 0.3 0.7 0.3 0.7 0.3 0.7 tck (avg) 8, a rtt dynamic change skew tadc 0.3 0.7 0.3 0.7 0.3 0.7 tck (avg) a write leveling timings first dqs/dqs rising edge after write leveling mode is programmed twlmrd 40 - 40 - 40 - nck 3 timing parameters by speed bin (continued) note: the following general notes from page 61 apply to table : a 800mhz 900mhz 1.0ghz parameter symbol min max min max min max units notes *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w \ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 77 h5tq2g63bfr dqs/dqs delay after write leveling mode is programmed twldqsen 25 - 25 - 25 - nck 3 write leveling setup time from rising ck, ck crossing to rising dqs, dqs crossing twls 170 - 130 - 120 - ps write leveling hold time from rising dqs, dqs crossing to rising ck, ck crossing twlh 170 - 130 - 120 - ps write leveling output delay twlo090909ns write leveling output error twloe020202ns timing parameters by speed bin (continued) note: the following general notes from page 61 apply to table : a 800mhz 900mhz 1.0ghz parameter symbol min max min max min max units notes *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w \ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 78 h5tq2g63bfr 0.1 jitter notes specific note a when the device is op erated with input clock jitter, this parameter needs to be derated by the actual terr (mper), act of the input clock, where 2 <= m <=12.(output deratings are relative to the sdram input cl ock.) for example, if the measured jitter into a ddr-800 sdram has terr (mper), act, min = -172 ps and terr (mper), act, max =+ 193 ps, then t dqsck, min (derated) = tdqsck, min - terr (mper), act, max = -400 ps - 193 ps = - 593 ps and tdqsck, max (derated) = tdqsck , max - terr (mper), act, min = 400 ps+ 172 ps = + 572 ps. similarly, tlz (dq) for ddr3-800 derates to tlz (dq), min (derated) = - 800 ps - 193 ps = - 993 ps and tlz (dq), max (derated) = 400 ps + 172 ps = + 572 ps. (caution on the min/max usage!) note that terr (mper), act, min is the minimum mea- sured value of terr (nper) where 2 <= n <=12 , and terr (mper), act, max is the maxi- mum measured value of terr (nper) where 2 <= n <= 12 specific note b when the device is op erated with input clock jitter, this parameter needs to be derated by the actual tjit (per), act of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr3-800 sdram has tck (avg), act = 2500 ps, tjit (per), act, min = - 72 ps and tjit (per), act, max = + 93 ps, then trpre, min (derated) = trpre, min + tjit (per), act, min = 0.9 x tck (avg), act + tjit (per), act, min (derated) = trpre, min + tjit ( per), act, min = 0.9 x tck (avg), act + tjit (per), act, min = 0.9 x 2500 ps - 72 ps =+ 2178 ps. similarly, tqh, min (derated) = tqh, min + tjit (per), act, min = 0.38 x tck (avg), act + tjit (per), act, min = 0.38 x 2500 ps - 72 ps = + 878 ps. (caution on the min/max usage!) specific note c these parameters are measur ed from a data strobe signal (dqs(l/u), dqs (l/u)) cross- ing to its respective clock signal (ck, ck ) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. tjit (per), tjit (cc), etc. ), as these are relative to the clock signal crossing. that is, these parameters should be met whether clock jitter is present or not. specific note d these parameters are measured from a data signal (dm(l/u), dq(l/u)0, dq(l/u)1, etc.) transition edge to its respective data strobe signal (dqs(l/u), dqs (l/u)) crossing. specific note e for these parameters, the dd r3 sdram device supports tnparam [nck] = ru {tparam [ns] / tck (avg) [ns]}, which is in clock cycles, assuming all input clock jitter specifications are satisfied. for example, the de vice will support tnrp = ru {trp / tck (avg)}, which is in clock cycles , if all input clock jitter specif ications are met. this means: for ddr3-800 6-6-6, of which trp = 15ns, th e device will support tnrp = ru {trp / tck (avg)} = 6, as long as the i nput clock jitter specif ications are met, i. e. precharge command at tm and active command at tm+6 is valid ev en if (tm+6 - tm) is less than 15ns due to input clock jitter. specific note f these parameters are specified per their average values, however it is understood that the following relationship between the average timing and the absolute instantaneous tim- ing holds at all times. (min and max of spec values are to be used fo r calculations in table . *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w \ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 79 h5tq2g63bfr timing parameter notes 1. actual value dependant upon measurement level definitions which are tbd. 2. commands requiring a locked dll are: read (and rap) and synchronous odt a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 80 h5tq2g63bfr where tsens = max (drttdt, drondtm) and vsens = max (drttdv, drondvm) define the sdram temperature and voltage sensitivities. for example, if tsens = 1.5% / o c, vsens = 0.15% / mv, tdriftrate = 1 o c / sec and vdriftrate = 15 mv / sec, then the interval between zqcs commands is calculated as: 22. n = from 13 cycles to 50 cycles. 23. tch (abs) is the absolute instantaneou s clock high pulse width, as measured fr om one rising edge to the following fall ing edge. 24. tcl (abs) is the absolute instantaneou s clock low pulse width, as measured from one falling edge to the following ris for all input signals the total tis (setup time) and tih (hold ti me) required is calculated by adding the data sheet tis (base) and tih (base) value (see table 11) to the tis and tih derating value (see table 12) respectively. example: tis (total setup time) = tis (base) + tis setup (tis) nominal slew rate for a rising signal is de fined as the slew rate between the last crossing of v ref(dc) and the first crossing of v ih(ac) min. setup (tis) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of vil (ac) max. if the actual signal is always earlier than the nominal slew rate line between shaded ?v ref(dc) to ac region?, use nominal slew rate for deratin g value (see figure 4). if the actual signal is later than the nominal slew rate line anywhere between shaded ?v ref(dc) to ac region?, the slew rate of a tangent line to the actual signal from the ac level to dc leve l is used for derating value (see figure 6). hold (tih) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vil (dc) max and the first crossing of v ref(dc) . hold (tih) nominal slew rate for a falling signal is defined as the slew rate between the last cross- ing of vih (dc) min and the first crossing of v ref(dc) . if the actual signal is always later than the nominal slew rate line between shaded ?dc to v ref(dc) region?, use nominal slew rate for derating valu e (see figure 5). if the actual signal is ear- lier than the nominal slew rate line anywhere between shaded ?dc to v ref(dc) region?, the slew rate of a tangent line to the actual signal from the dc level to v ref(dc) level is used for derating value (see figure 6). for a valid transition the input signal has to remain above/below v ih/il(ac) for some time t vac (see table 14). zqcorrection (tsens x tdriftrate)+ ( vsens x vdriftrate) -------------------------- ------------------------------ ----------------------------- ----------------------- 0.5 (1.5 x 1)+(0.15 x 15) ------------------------------- ----------------------- 0 . 1 3 3 1 2 8 m s == *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w \ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 81 h5tq2g63bfr although for slow slew rates the total setup time might be negative (i.e. a valid input si gnal will not have reached v ih/il(ac) at the time of the rising clock transition) a valid input si gnal is still required to complete the transition and reach v ih/il(ac) . for slew rates in between the values listed in table 12, the derating values may obtained by linear interpolation. these values are typically not subject to production te st. they are verified by design and characterization. table 11 - add/cmd setup and hold base-values for 1v/ns note: - (ac/dc referenced for 1v/ns dq-slew rate and 2 v/ns dqs slew rate) - the tis (base) ac150 specifications are adjusted from the tis (base) specification by adding an additional 100 ps tis, tih derating in [ps] ac/dc based ac175 threshold -> vih (ac) = vref (dc) + 175mv, vil (ac) = vref (dc) - 175mv ck,ck differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih cmd / add slew rate v/ns 2.0 88 50 88 50 88 50 96 58 104 66 112 74 120 84 128 100 1.55934593459 34 67427550835891689984 1.00 0 0 0 0 0 8 8 1616242432344050 0.9-2 -4 -2 -4 -2 -4 6 4 1412222030303846 0.8 -6 -10 -6 -10 -6 -10 2 -2 10 6 18 14 26 24 34 40 0.7 -11 -16 -11 -16 -11 -16 -3 -8 5 0 13 8 21 18 29 34 0.6 -17 -26 -17 -26 -17 -26 -9 -18 -1 -10 7 -2 15 8 23 24 0.5 -35 -40 -35 -40 -35 -40 -27 -32 -19 -24 -11 -16 -2 -6 5 10 0.4 -62 -60 -62 -60 -62 -60 -54 -52 -46 -44 -38 -36 -30 -26 -22 -10 *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w \ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 82 h5tq2g63bfr table 13 - derating values tis/tih - ac/dc based tis, tih derating in [ps] ac/dc based alternate ac150 threshold -> vih (ac) = vref (dc) + 150mv, vil (ac) = vref (dc) - 150mv ck,ck differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih cmd / add slew rate v/ns 2.07550755075 50 83589166997410784115100 1.55034503450 34 58426650745882689084 1.00 0 0 0 0 0 8 8 1616242432344050 0.9 0 -4 0 -4 0 -4 8 4 16 12 24 20 32 30 40 46 0.8 0 -10 0 -10 0 -10 8 -2 16 6 24 14 32 24 40 40 0.7 0 -16 0 -16 0 -16 8 -8 16 0 24 8 32 18 40 34 0.6 -1 -26 -1 -26 -1 -26 7 -18 15 -10 23 -2 31 8 39 24 0.5 -10 -40 -10 -40 -10 -40 -2 -32 6 -24 14 -16 22 -6 30 10 0.4 -25 -60 -25 -60 -25 -60 -17 -52 -9 -44 -1 -36 7 -26 15 -10 slew rate [v/ns] t vac @ 175 mv [ps] t vac @ 150 mv [ps] min max min max > 2.0 75 - 175 - 2.0 57 - 170 - 1.5 50 - 167 - 1.0 38 - 163 - 0.9 34 - 162 - 0.8 29 - 161 - 0.7 22 - 159 - 0.6 13 - 155 - 0.5 0 - 150 - < 0.5 0 - 150 - *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w \ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 83 h5tq2g63bfr figure 3 - illustration of nominal slew rate and t vac for setup time t ds (for dq with respect to strobe) and t is (for add/cmd with respect to clock). v ss setup slew rate setup slew rate rising signal falling signal tf tr v ref(dc) - v il(ac) max tf = v ih(ac) min - v ref(dc) tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max nominal nominal slew rate vref to ac region vref to ac region tvac tvac slew rate tdh tds dqs dqs tdh tds ck ck tis tih tis tih note: clock and strobe are drawn on a different time scale. *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w \ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 84 h5tq2g63bfr figure 4 - illustration of nomi nal slew rate for hold time t dh (for dq with respect to strobe) and t ih (for add/cmd with respect to clock). v ss hold slew rate hold slew rate falling signal rising signal tr tf v ref(dc) - v il(dc) max tr = v ih(dc) min - v ref(dc) tf = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max nominal slew rate nominal slew rate dc to v ref region dc to v ref region tdh tds dqs dqs tdh tds ck ck tis tih tis tih note: clock and strobe are drawn on a different time scale. *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w \ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 85 h5tq2g63bfr figure 5 - illustration of tangent line for setup time t ds (for dq with respect to strobe) and t is (for add/cmd with respect to clock). v ss tdh setup slew rate setup slew rate rising signal falling signal tf tr tangent line [ v ref(dc) - v il(ac) max] tf = tangent line [v ih(ac) min - v ref(dc) ] tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tds tangent tangent v ref to ac region v ref to ac region line line nominal line nominal line tvac tvac dqs dqs tdh tds ck ck tis tih tis tih note: clock and strobe are drawn on a different time scale. *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w \ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 86 h5tq2g63bfr figure 6 - illustration of tangent line for hold time t dh (for dq with respect to strobe) and t ih (for add/cmd with respect to clock). v ss hold slew rate tf tr tangent line [v ih(dc) min - v ref(dc) ] tf = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tangent tangent dc to v ref region dc to v ref region line line nominal line nominal line falling signal hold slew rate tangent line [ v ref(dc) - v il(dc) max] tr = rising signal tdh tds dqs dqs tdh tds ck tis tih tis tih n o t e: cl oc k an d st ro b e are d rawn on a different time scale. ck *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w \ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 87 h5tq2g63bfr data setup, hold and slew rate derating for all input signals the total tds (setup time) and tdh (hold time) required is ca lculated by adding the data sheet tds (base) and tdh (base) value (see table 15) to the dtds and dtdh (see table 16) derating value respectively. example: tds (total setup time) = tds (base) + dtds. setup (tds) nominal slew rate for a ri sing signal is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of v ih(ac) min. setup (tds) nominal slew rate for a falling sign al is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of v il(ac) max (see figure 7). if the actual sign al is always earlier than the nomi- nal slew rate line between shaded ?v ref(dc) to ac region?, use nominal slew rate for derating value. if the actual signal is later than the nominal slew rate line anywhere between shaded ?v ref(dc) to ac region?, the slew rate of a tangent line to the actual signal from the ac level to dc le vel is used for derating value (see figure 9). hold (tdh) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v il(dc) max and the first crossing of v ref(dc) . hold (tdh) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ih(dc) min and the first crossing of v ref(dc) (see figure 8). if the actual signal is always later than the nominal slew rate line between shaded ?dc level to v ref(dc) region?, use nominal slew rate for dera ting value. if the actual signal is earlier than the nominal slew rate line anywhere between shaded ?dc to v ref(dc) region?, the slew rate of a tangent line to the actual signal from the dc level to v ref(dc) level is used for derating value (see figure 9). for a valid transition the input si gnal has to remain above/below v ih/il(ac) for some time t vac (see table 17). although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached v ih/il(ac) at the time of the rising clock transition) a valid input sign al is still required to complete the transition and reach v ih/il(ac) . for slew rates in between the values listed in the tables the derating values may obtained by linear interpolation. these values are typically not subject to production test. they are verifi ed by design and characterization. table 15 - data setup and hold base-values note: (ac/dc referenced for 1v/ns dq-sle w rate and 2 v/ns dqs-slew rate) units [ps] 800mhz 900mhz 1.0ghz reference tds (base) 10 0 tbd v ih/l(ac) tdh (base) 45 45 tbd v ih/l(dc) *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w \ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 88 h5tq2g63bfr table 16 - derating values tds/tdh - ac/dc based table 17 - required time t vac above vih (ac) {below vil (ac)} for valid transition tds, dh derating in [ps] ac/dc based a a.cell contents shaded in red are defined as ?not supported?. dqs, dqs differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh dq slew rate v/ns 2.0 88 50 88 50 88 50 - - - - - - - - - - 1.5 59 34 59 34 59 34 67 42 - - - - - - - - 1.0 0 0 0 0 0 0 8 8 16 16 - - - - - - 0.9 - - -2 -4 -2 -4 6 4 14122220 - - - - 0.8 - - - - -6 -10 2 -2 10 6 18 14 26 24 - - 0.7 - - - - - - -3 -8 5 0 13 8 21 18 29 34 0.6 - - - - - - - - -1 -10 7 -2 15 8 23 24 0.5 - - - - - - - - - --11-16-2-6 510 0.4 - - - - - - - - - - - - -30 -26 -22 -10 slew rate [v/ns] t vac [ps] min max > 2.0 75 - 2.0 57 - 1.5 50 - 1.0 38 - 0.9 34 - 0.8 29 - 0.7 22 - 0.6 13 - 0.5 0 - < 0.5 0 - *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w \ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 89 h5tq2g63bfr figure 7 - illustration of nominal slew rate and t vac for hold setup t ds (for dq with respect to strobe) and t is (for add/cmd with respect to clock). v ss setup slew rate setup slew rate rising signal falling signal tf tr v ref(dc) - v il(ac) max tf = v ih(ac) min - v ref(dc) tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max nominal nominal slew rate vref to ac region vref to ac region tvac tvac slew rate tdh tds dqs dqs tdh tds ck ck tis tih tis tih note: clock and strobe are drawn on a different time scale. *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w \ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 90 h5tq2g63bfr figure 8 - illustration of nomi nal slew rate for hold time t dh (for dq with respect to strobe) and t ih (for add/cmd with respect to clock). v ss hold slew rate hold slew rate falling signal rising signal tr tf v ref(dc) - v il(dc) max tr = v ih(dc) min - v ref(dc) tf = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max nominal slew rate nominal slew rate dc to v ref region dc to v ref region tdh tds dqs dqs tdh tds ck ck tis tih tis tih note: clock and strobe are drawn on a different time scale. *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w \ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 91 h5tq2g63bfr figure 9 - illustration of tangent line for setup time t ds (for dq with respect to strobe) and t is (for add/cmd with respect to clock). v ss tdh setup slew rate setup slew rate rising signal falling signal tf tr tangent line [ v ref(dc) - v il(ac) max] tf = tangent line [v ih(ac) min - v ref(dc) ] tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tds tangent tangent v ref to ac region v ref to ac region line line nominal line nominal line tvac tvac dqs dqs tdh tds ck ck tis tih tis tih note: clock and strobe are drawn on a different time scale. *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w \ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 92 h5tq2g63bfr figure 10 - illustration of tangent line for hold time t dh (for dq with respect to strobe) and t ih (for add/cmd with respect to clock). v ss hold slew rate tf tr tangent line [v ih(dc) min - v ref(dc) ] tf = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tangent tangent dc to v ref region dc to v ref region line line nominal line nominal line falling signal hold slew rate tangent line [ v ref(dc) - v il(dc) max] tr = rising signal tdh tds dqs dqs tdh tds ck ck tis tih tis tih note: clock and strobe are drawn on a different time scale. *33ed5962-ee6c* i y w z z ^ v x ^ _ u x w [ u y u y z [ v y w x w t w _ t y ] g w ` a w \ a pcpcwm_4828539:wp_0000002wp_0000002 apcpcwm_4828539:wp_0000002wp_0000002 rev. 0.5 / aug. 2010 93 h5tq2g63bfr 12. package dimensions 12.1 package dimension(x 16); 96ball fine pitch ball grid array outline a1 corner index area (3.250) (2.250) 9.000 0.100 13.000 0.100 0.340 0.050 1.100 0.100 987 21 a b c d e f g h j k l m n 0.800 x 8 = 6.400 0.800 1.600 0.800 x 15 = 12.000 0.800 1.600 0.500 0.100 top view bottom view side view 3.0 x 5.0 min flat area a1 ball mark 3 p r t 96 x 0.450 0.050 |
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